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LMK04832EVM: Issue of chaging clkin1 frequency

Part Number: LMK04832EVM
Other Parts Discussed in Thread: LMK04832

Hi,

We were using the LMK04832EVM with a 100 MHz clkin1 input ,
replacing the original default configuration clkin1 122.88 MHz.

Once we changed frequency from 122.88 MHz to 100MHz, the status LD1 goes off.
Though we've tried set the CLKin1 frequency from 122.88 MHz to 100MHz in TICS pro (CLKinX  Control page, PLL1 and 2  page and Clock Outputs page),
it still couldn't get the acurate output frequency and PLL Lock.

Is it possible to get the two different output frequency(100MHz and 122.88MHz) which both are syncornized to the input 100MHz?
Which registers need to be set in TICS Pro to get the  above request?

Thank you !
Best regards,
Alan

  • Hi Alan,

    LMK04832 has an integer N & R dividers and EVM has 122.88MHz VCXO on-board at OSCin inputs.

    When you change the CLKin1 input frequency to 100MHz, it doesn't find the integer N value and unlock the PLL. I believe, you are using in dual PLL mode and not getting lock detect.

    LMK04832 can be operate in single PLL mode (PLL2) using the reference at any of the input pins. Select PLL2 RCLK MUX at PLL1 CLKinX configuration, CLKin inputs reaches to PLL2 and can operate in single PLL mode.

    100MHz and 122.88MHz both can't be generate with single device.

    Regards,
    Ajeet Pal

  • Hi Ajeet,

    Thanks for your reply,
    So if we use single PLL mode (PLL2),
    while input CLKin1 set to 100MHz and 122.88 MHz VCXO remained.
    Is it avalible to generate 100 MHz at output? 

    By the way,
    I'we tried to select PLL2 RCLK MUX at PLL1 CLKinX configuration but the status_LD2 still goes off. 
    And the output frequency shows on the TICS Pro is not same as the frequency I measured on oscilloscope.
    Is there any else registers need to be set?

    Thank you!
    Best regards,
    Alan 


  • Hi Alan,

    So if we use single PLL mode (PLL2),
    while input CLKin1 set to 100MHz and 122.88 MHz VCXO remained.
    Is it avalible to generate 100 MHz at output?

    Yes, PLL2 can take any of the inputs based on the setting CLKin_SEL_MANUAL and PLL2_RCLK_MUX for input selection.

    For PLL2 lock with 100MHz input, need to set the VCO frequency and lock the PLL.

    Attached is the updated .tcs file for 100MHz input and output frequency. Please try with this.

    LMK04832EVM_100M_CLKin1_PLL2.tcs

    Regards,

    Ajeet Pal