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LMK04828: CLKIN1 input leaking on CLKIN0

Nik
Prodigy 110 points
Part Number: LMK04828


CLKIN0 got uFL connector so the external clock can be fed to LMK04828. 40MHz differential clock is connected at CLKIN1p/n (pin 34, 35). 

I am observing 40Mhz clock from CLKIN1 is leaking on CLKIN0 while no input signal at CLKIN0. What could be the reason to observe clock on CLKIN0?

Is there any LMK04828 setting required to avoid this?

  • 0
    TI__Mastermind 33970 points

    Hello Nikhil,

    CLKin0 and CLKin1 share a power supply, and the internal LDO PSRR begins to decline sharply past 10MHz. Additionally, since the CLKin pins are high impedance, there is some degree of high-frequency coupling between these pins when only one set is being actively driven - in theory this should be significantly attenuated due to the presence of 50Ω termination at the pins, but uneven capacitive coupling to each differential leg can still toggle the input. So there are multiple paths by which a higher-frequency clock signal could couple into a temporarily-unused input.

    Selecting CLKin1 manually is a reliable way to ensure CLKin1 is selected, but requires some programming or external intervention through pin control to switch to CLKin0 if needed. But if automated selection is required, some other method may be necessary to ensure CLKin0 is not toggling. CMOS signals DC-coupled in MOS mode input are theoretically the best-case for noise rejection, but would require a CMOS signal (or at least something with CMOS signal levels) even while no signal is being driven by the uFL connector - maybe this means an additional CMOS buffer to set the no-input levels. Bipolar mode switches AC-coupling in at the device level, so it will still be susceptible to noise coupling regardless of DC or AC coupling; in any case, DC-coupling bipolar mode on LMK04828 is not recommended.

    Regards,

    Derek Payne