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LMK04832: Sync clocks creation using LMK04832 and LMX2582 for different ADCs and DAC

Part Number: LMK04832
Other Parts Discussed in Thread: LMX2582,

Hi, we would like to create four clocks for our application using TI LMK04832 and LMX2582 chips, as described in attached sheet.
Could you help to take a look of it and let us know if the scheme works. If yes, could you let us know how to make configuration in registers of the chips?


  • Hi Jimmy,

    Ideally, the attached clock scheme should work fine, as it was already worked in distribution mode (LMK04832).

    As your clock required frequencies are not integer division of 3.2GHz, LMK04832 needs to be operate in PLL mode.

    I would need to verify it and will update you soon.


    Ajeet Pal

  • Hi Jimmy,

    I believe I recognize this discussion from an email conversation with Neeraj, where we suggested using the LMK04832 internal VCO at 3000MHz to generate the 500MHz and 250MHz requirements. For completeness (in case anyone else is reviewing with similar questions), I will also add my email response to the E2E thread and mark as resolved. We can continue support through E2E or through email per your preference.

    You can get 200MHz SYSREF (divide-by-16), but not 160MHz SYSREF (divide-by-18.75), from 3000MHz VCO on LMK04832. LMK04832 only has integer channel dividers and integer SYSREF divider.

    N2 divider has a prescaler that must be set, but it is still possible to achieve divide-by-15 by setting the prescaler to either 3 or 5, and setting N2 to either 5 or 3, respectively. Additionally, the outputs still receive 3000MHz at the input to each channel divider, and channel dividers support divide-by-1, so LMK04832 can support 3GHz output. There is even a high-performance bypass mode which can utilize high-amplitude CML output stages, since other output formats will see some attenuation at higher frequencies.

    You cannot use LMX2582 with one output set to 3.2GHz and the other set to 200MHz. 3.2GHz is below the minimum output frequency for the VCO, so the channel divider would need to be active and set to divide-by-2. This conflicts with the 200MHz output, which would need to use the channel divider at divide-by-32. Refer to LMX2582 datasheet, figure 19 and figure 20, for a detailed block diagram explaining why this is not possible.

    That said, it is not necessary to drive 200MHz into LMK04832 through the LMX2582 – instead, just double the 100MHz oscillator through the OSCin port and use this as the reference to PLL2 (OSCin->OSCout and OSCin->PLL2 R paths are available simultaneously).


    Derek Payne