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LMK04832EVM: External CLK setting

Part Number: LMK04832EVM

Hi teams,

About step2 in default setting: Connect a reference clock to the CLKin1* port from a signal generator or other source. Use 122.88 MHz for default configuration.

Exact frequency and input port (CLKin0/CLKin1) depends on programming.

If we want to use external source 10MHz on CLKIn port, and expect to get CLKOut = 122.8MHz, also make sure that the two frequencies are locked.

What are the settings on TICS PRO?


  • Hello Ryan,

    Assuming you keep the dual-loop configuration and use the VCXO as PLL1 feedback oscillator, GCD(122.88MHz, 10MHz) = 80kHz. So you would set the phase detector to 80kHz, the R-divider to 10M/80k = 125, and the N-divider to 122.88M/80k = 1536. You will need to redesign the loop filter for stability and optimal phase noise performance - please check PLLatinum Sim tool to determine the optimal values.


    Derek Payne