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LMK5B12204: About the clock register setting of the LMK5B12204 chip

wu Lance
Prodigy 40 points
Part Number: LMK5B12204

Hi：Ti

The following problems are currently encountered:

Hardware connection mode: the 6th pin PRIREF_P of this chip is connected to the clock frequency of 6.144Mhz, the 7th pin PRIREF_N is pulled down to the ground; the 31st pin XO_P is connected to the TCXO or OCXO frequency 24Mhz, the 32nd pin XO_N is pulled down to the ground;

1): If using DPLL+APLL1 (cascade APLL mode), how to set the LMK5B12204 register?

2) If using DPLL+APLL (ByPass mode), how to set the LMK5B12204 register?

3) Which mode is used to output the smallest frequency jitter, the best stability and accuracy? If this mode has the best output, how to set the LMK5B12204 register?

4) If the chip enters EEPROM+I2C mode or ROM+I2C mode after startup, does the register setting need to be written to EEPROM or ROM or can it be written directly to SRAM? If it must be written in EEPROM or ROM, how to start the chip from EEPROM or ROM? Is it possible to initialize the registers every time the chip is powered on without starting from EEPROM or ROM? If it is necessary to write to EEPROM or ROM, how to set the register to write to EEPROM or ROM?

5) How to use TISC PRO software tool? Is there a detailed operating instruction document?

Please reply as soon as possible, thank you!

  • 0
    TI__Expert 6140 points

    Hi Wu,

    I believe you have another thread asking similar questions, so please mark one as closed and we can address the questions in one place.

    As mentioned in other thread, TICSpro should be used to generate any and all configurations. This is software that you will provide some basic inputs into and the will then run some calculations and give you the register programming best suited for your needs.

    1. Use TICSpro.

    2. What is meant by bypass mode here? Bringing the reference output all the to a clock output pin? The XO output? These are for test purposes really... clarify what you mean by bypass mode please.

    3. DPLL loop bandwidth (LBW) is 4 kHz at max setting; it can be set to something significantly smaller than that and generally it's somewhere around 10 Hz or 100 Hz. Either way DPLL application will not impact jitter performance in the 12 kHz - 20 MHz range. DPLL application will have device locked to reference input, whatever the ppm offset is. APLL only application you're relying on XO for the stability. For setting registers follow instructions in the wizard in TICSpro.

    4. It is recommended that EEPROM mode is used for all use cases. The part will come with a generic factory EEPROM. You can program the EEPROM to whatever configuration of your choosing and on subsequent powerups device will boot up in your configuration. There are instructions provided in the datasheet on how to program the EEPROM. The EEPROM can be programmed upto 100x so you definitely can program configuration and play with the part before finalizing your decision.

    5. TICSpro wizard tab uses a step by step question and answer type of a flow with instructions on every single page. This should be used in order to arrive at the configuration for your needs.

    Thanks and regards,

    Amin

  • 0 in reply to Amin Eshraghi
    Prodigy 40 points

    Hi:Amin

    APLL ByPass mode means to use only DPLL, not APLL1 or APPL2; direct DPLL output, APLL does not require any settings;

    At present, the reference frequency of XO input is set to 25Mhz through TISC PRO tool. DPLL mode is prohibited. Set OUTPUT output directly, and measure OUTPUT3 to output 25Mhz. Why is the maximum voltage amplitude only 700m instead of 3.3v?

  • 0 in reply to wu Lance
    Prodigy 40 points

    Hi:Amni

     After setting the frequency through the TISC PRO software tool, how to export the register? Export register value, File->Export hexadecimal register value, the exported file shows more than 300 registers, do I need to write them one by one?

  • +1 in reply to wu Lance
    TI__Expert 6140 points

    Hi Wu,

    On your first question, device requires and XO - DPLL only mode will not function. In order to produce output clocks APLL has to be up and running and it can only use XO input as reference.

    Device provides typical LVPECL, LVDS, CML swing level and HCSL on all channels. CH2 and CH3 also have the option for LVCMOS output type but this is also 1.8V LVCMOS and not 3.3V. You will need to use a buffer or a level translator in order to achieve 3.3V swings, as it's not supported in any of the output type. Please review the clock output section of the datasheet.

    Yes, this is a very complex device hence no manual programming is ever recommended and we have software and calculates and programs registers. The file exported is what is required to update the register settings. There are simple updates, for example if all you're doing is changing the output divider from the factory EEPROM image then that would be one register right. But I see you're using 25 MHz XO so already you will have many changes so I recommend sticking with the file.

    Thanks and regards,

    Amin