In our design, the reference clock comes in at a very low power level as a 50Ohm signal. As the clock-input of the LMX is of the CMOS-variety, the goal is to use a high impedance signal (not 50Ohm terminated, but higher) just requiring the use of an amplifier with a high voltage-amplification but not waste space/resources with a high current amplification aswell, since the power would only be wasted in the termination and the amplifier would be located less than 10mm from the LMX, guaranteeing signal integrity.
I was wondering what the actual impedance of the input was and wether there was a maximum recommended impedance to be used or if there were other suggestions on how to handle low reference-clock-power-levels. The current temporary solution is to use a 30dB amplifier to boost the 50Ohm terminated signal to 0dBm 50Ohm terminated on the LMX, but the amplifier is huge and wastes a lot of power.