Part Number: LMK05318B
What is the EEPROM configuration/initialization time, i.e. the time from internal POR to clocks are stable at outputs when in I2C/EEPROM mode.
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Part Number: LMK05318B
What is the EEPROM configuration/initialization time, i.e. the time from internal POR to clocks are stable at outputs when in I2C/EEPROM mode.
Hello,
If this is with regards to bootup from EEPROM and lock + stable output clocks, this would be the APLL lock time. This is not specified but ~10 ms is a fair number to use, should provide more than enough guardband. Internal POR is established once core supply reaches min Vdd requirement (3.3V - 10%) with PDN pin pulled high (if floating, it will be pulled high internally)
Regards,
Amin
Sure. I'm not sure what you mean by EEPROM initialization of registers, that 10 ms timeframe is with regards to full lock of the configuration, EEPROM would have to set the registers much faster than that because that is time for the APLL to calibrate and lock.
If your question is with regards to EEPROM programming, committing the full SRAM to EEPROM takes about ~230 ms.
Regards,
Amin