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LMK03806: LMK03806 operation error

JH Shin
Guru 12875 points

Part Number: LMK03806

Hello,

My customer is using the LMK03806 with the following conditions on a custom board.

    - OSCIN : 30.72MHz input(single ended)

    - Output frequency : 491.52MHz

    - The register settings are as in the TICS Pro file below.

LMK03806B_test1.tcs

The PLL was unlocked and the the 491.52MHz output clock could not be obtained.

Please advise what the problem is.

Thank you.

JH

  • 0
    TI__Mastermind 18070 points

    Hi JH,

    It's very likely due to unstable loop. The PFD frequency is too low. As a result, the default loop configurations won't apply and you'll need to set new loop component values. You can do so in "PLLatinum sim" software, or you can simply change the input frequency to for example 12.288MHz or 24.576MHz, if that's doable.

    Regards,
    Hao

  • 0 in reply to Hao Z
    Guru 12875 points

    Hi Hoa,

    Thanks for your help.

    Could you please provide a sample simulation file of the PLLatinum sim with the your recommended conditions?

    The customer wants to see that the LMK03806 has 491.52MHz clock outputs with 30.72MHz reference clock.

    Thanks a lot.

    JH

  • 0 in reply to JH Shin
    TI__Mastermind 18070 points

    Hi JH,

    I relooked at the configuration and found that the pre-division of reference frequency is unnecessary. You can do the following instead:

    After changing to above configuration, the PLL should be able to lock with default loop settings. You can still use PLLatinum sim to further optimize loop settings. Here are the buttons and parameters you can play with. The instructions can be found when clicking the question mark.

    For example, to achieve stable loop, the phase margin should be around 70 degrees.

    Regards,
    Hao