Part Number: CDCLVP111-SP
Hi Team,
We are currently using CDCLVP111-SP to drive multiple circuitry and some of these circuits are not being powered at the same time. There's a circuit to prevent driving the clock buffer while still unpowered during the boot-up sequence.
Our question is particularly on the power-off sequence. We are aware of the <0.5V limit for the clock inputs while unpowered, but is there a maximum time the CDCLVP111-SP can be driven by an LVDS signal while not powered?
Kind Regards,
Jejomar
