Other Parts Discussed in Thread: LMK05318B, LMK5B12204
I setup the LMK05318B evaluation board to generate a 140MHz signal using APLL2 on OUT0 and a 100MHz signal using APPL1 on OUT7 with a 10MHz clock on the primary reference input. The performance of the evaluation board is acceptable to me with no measurable spurs and a phase noise at a 10kHz offset of -137dBc on the 100MHz output using APLL1. I now would like to verify performance with a more readily available XO than the one on the evaluation board.
I replaced the 48.0048MHz XO that is on the evaluation board with the 24.576MHz Kyocera KC2520Z24.5760C15XXK and stepped through the TICS Pro Wizard using the new XO frequency of 24576000Hz. I used the suggested frequency plan and used the Matlab script to set the DPLL in the same way as for my original design with the 48.0048MHz XO. However, I now measure very high phase noise and lots of spurs on both outputs. The worst case spurs are at +/-1590Hz from the carriers at a level of -60dBc. The Status page of the TICS Pro application indicates that all PLLs are locked and the outputs are at the correct frequencies of 100 and 140MHz. I've tried going through the Wizard several times with slightly different output configurations and I still get this poor performance. I would like to know if there are any considerations in changing the XO frequency without degrading performance that I may have missed.