CDCS502: Center frequency variation

Yusuke Mukuno

Part Number: CDCS502

Hi Expert,

Is there any variation of output frequency that is due to IC performance? (if SSC is not used(+/-0%), and if the input clock is defined as having no variation)

If yes, Is it change by x1 or x4 setting?

Thanks

Muk

over 3 years ago

+1 Julian Hagedorn over 3 years ago

TI__Mastermind 20900 points

Hello Muk,

in x1 setting the device acts as buffer and follows the input frequency. In x4 mode the internal PLL multiplies the input by 4. The PLL is phase and frequency locked to the input.

Variations of center frequency are coming only from the input.

regards,

Julian

0 Yusuke Mukuno over 3 years ago in reply to Julian Hagedorn

TI__Expert 7395 points

Thanks Julian,

Clock & timing

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CDCS502: Center frequency variation