Hi Ti-Support,
I have just a vewry simple question (I think)
I want to make a very simple clock divider for an application with an D-Fli-Flop. SN74AUC2G80DCUR
The circuit is very simple and work theoretical, but not practical ;-)
The output from the D-FF will be connect to the D-Input and so on.
For short it do not work, I guess I need some delay for the feedback (RC combination).
Or is this not possible with this device.
Regards
sascha
Hi Sascha,
At the device's maximum supply (2.5V), the data input has to hold for 0.5ns.
That's not much, so just adding some resistance between the Q\ output and the D input should be sufficient enough for the required delay (the input has some capacitance). I'd try a 220 ohm resistor to start and only increase if needed.
I noticed that your supply is at 3.3V -- can't see the supply for the AUC device, but I'm assuming it's also at 3.3V. While that shouldn't damage the device, we can't guarantee performance and most likely the hold time is longer at that voltage.
Please let me know if I can be of further assistance.
