LMX2572: What does phase synchronization (SYNC pin) mean if two devices have a different fout

Andrew,

Summarizing the paragraphs below: While this isn't strictly impossible with multi-frequency Category 3 SYNC, it may be too daunting to reliably attempt. If you have the option, I recommend using RF DACs like DAC38RF80 as DDSs instead - you get better noise floor, no fractional spurs, and fast well-characterized frequency hopping times.

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Regarding LMX2572 synchronizing two separate output frequencies:

Conceptually you could achieve what you're after, thanks to the MASH_SEED. As long as you have no frequencies that fall under Category 4 SYNC, you should be able to treat every SYNC event as a Category 3 SYNC, synchronize to the same OSCin cycle, and at some time afterward (determined by MASH_RST_COUNT) the two outputs will share a constant phase relationship. The trick is, because of differences in analog settling time and tolerances on loop filter components, the exact time when this alignment can be achieved is not predictable. The most you can say is, at some point after MASH_RST_COUNT phase detector cycles, a reproducible phase offset between the two synthesizers at different frequencies could be achieved.

To hopefully clarify my point: let's say that you want an isochronous edge on both the 100MHz and 105MHz clocks, such that every 20 periods of the 100MHz clock or every 21 periods of the 105MHz clock (i.e. every 5MHz)  you would get an isochronous edge. There does exist a MASH_SEED value that establishes this phase relationship between the two clocks after a SYNC event. The SYNC will be triggered, dividers will be reset, the MASH will be held in reset, the PLL will temporarily behave like an integer PLL, and the output frequencies will move up and down for a little while as the VCOs settle at integer values; then, at some point in the future (after at least MASH_RST_COUNT phase detector clock cycles), the MASH re-enables, the PLL experiences a frequency transient from the integer frequency to the fractional frequency, and after the output settles to its new frequency you should be able to see this isochronous edge phase relationship. In fact, this should be possible for any other relationship that could be established between the two clocks.

You are also establishing a repeatable phase offset between the OSCin clock and the output clocks. To keep things simple, let's say OSCin is 5MHz for both devices (performance concerns aside). If you want, you can guarantee that after a SYNC event and waiting at least MASH_RST_COUNT phase detector clock cycles + some settling time, the 100MHz/105MHz output and the 5MHz OSCin are isochronous as well. If the exercise is repeated with a 100MHz OSCin and a 5MHz GCD clock derived from/retimed to that OSCin, such that you generate SYNC events at the isochronous 5MHz GCD, it should conceptually be possible to know the phase of the output with respect to the derived GCD, and by extension it should be possible to count some number of OSCin cycles after the SYNC event and predict which 100MHz OSCin edges are isochronous with both output clocks.

If the delay through the mixer is known, it should likewise be possible to guarantee a specific phase of the mixing product of the two synthesizers relative to the input-derived GCD, and therefore relative to some number of input clock cycles.

The remaining obstacle: due to tolerances in the loop filter, charge pump current variation over PVT, etc, you don't know how long after MASH_RST_COUNT phase detector cycles it will take to reach the predicted phase offset. You can make an educated guess: the SYNC event holds the MASH in reset state, so immediately after the SYNC event the device will behave as an integer PLL for MASH_RST_COUNT phase detector cycles. After MASH_RST_COUNT phase detector cycles, the MASH reset is released, and your PLLs experience a frequency transient as they move from the integer frequency to the fractional frequency at the VCO. You can sometimes model this transient in PLLatinum Sim based on the nominal loop filter values, charge pump current, starting/ending frequencies, and VCO characteristics. But if you already started with an integer relationship between frequencies (e.g. 100MHz phase detector, 100MHz output), we have no model which describes the time for the phase offset programmed by the MASH_SEED to take effect. We can model frequency transients; we can't model phase transients. (But maybe we could, if we knew how? Hmm... perhaps I will consult our PLLatinum Sim maintainer about if such a model exists).

So, to summarize: You can establish an arbitrary phase relationship between two synthesizers. You cannot always know the time required to establish the reproducible phase offset between your two synthesizers. You only know that, at some point in the future following your SYNC event, which you can estimate but not conclusively calculate, your arbitrary phase relationship will be established. Given that you are open to using full assist calibration (which requires per-device lookup tables) to speed up your frequency generation, I am not sure your application can tolerate the delay required for the phase relationship to be established using this method. Even assuming the time delay to enact the SYNC is acceptable, you would also need to prepare some mechanism to generate your mixing product with a fixed phase relationship to the GCD of the input and outputs (in this case conveniently your 5MHz mixing product is your GCD, so it's not so hard... but if the GCD of input and outputs is not also the mixing product (or a multiple of the mixing product), this probably requires a separate PLL, and could take a very long time if the GCD frequencies are extremely low e.g. millihertz - hopefully this is beyond your problem scope). Then you must somehow compare it with the mixer output. Finally, you need some way to servo the MASH_SEEDs in both devices to achieve your required phase relationship for every frequency pair you plan to use, including calibrating out skew variation across voltage/temperature between each pair of synthesizers.

This isn't strictly impossible...

If you have the option, I recommend you use high-speed DACs to do direct digital synthesis. The noise floor will be better, you won't have any fractional spurs, and the DACs can frequency hop to precise phases with well-characterized (and comparatively short!) delay using the same kind of simultaneous SYNC event. Though it isn't advertised, the DAC38RF80 or similar devices can be used as DDS DACs without much trouble.

Regards,

Derek Payne