• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 20 subscribers
  • Views 397 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

using CDCM7005 for sceintific controlled clock

ACQUASANTA ANTONIO
Prodigy 40 points
Other Parts Discussed in Thread: CDCM7005

Hi friend

I have few problem at using CDCM7005 because I haven't great experience in PLL e similar

My customer had choose CDCM7005 for a design a scientific  RTC clock

because a RTC must to  work in every situation a source start is a high precsion couple of  cesium clock at 10Mhz

Idea is that when one of this failure system will be change at second cesium source ( without any glitch and with a maximum accepted delay of  1/2 cycle

So I thisnk that is possible to use this two source for syncro a VCXO using CDCM7005 ;

Just only for test I 'm in using a kit of CDCM7005 with a 491,52 Mhz  with output divide for 16

I'm try to program a N register with 1020 ( and MUX choose divide for 16) and M reg with a value 332 ( with a 10Mhz put in primary ref)

for to have a same freq in PFD

But i don't see a output on Y0A syncronized with my primary source

Can you help me ? probabily for no much expereince I don't understund well

 

  • 0
    TI__Expert 4150 points
    I am not sure about your setup. If you use a 491.52MHz VCXO and divide it by 16, you expect the output frequency ot be 30.72MHz, not 10MHz. Therefore, you can not see if the VCXO is locked or not.
     
    I think you need to set your M/N divders such that you divide the 491.52MHz with 6144 and 10MHz with 125 to run the PFD frequency at 80kHz.
     
    Hope this helps, best regards, Fritz

  • 0 in reply to Fritz
    Prodigy 40 points

    Fritz said:
    I am not sure about your setup. If you use a 491.52MHz VCXO and divide it by 16, you expect the output frequency ot be 30.72MHz, not 10MHz. Therefore, you can not see if the VCXO is locked or not.
     
    I think you need to set your M/N divders such that you divide the 491.52MHz with 6144 and 10MHz with 125 to run the PFD frequency at 80kHz.
     
    Hope this helps, best regards, Fritz

    Fritz

    thanks a lot for your feedabck

    I tried with 6144 and 125 but don't  results are the same ;

    Output on Y0A is 30,72Mhz ( that is OK because I choosed divide for 16 ; for try to syncronize I had choose divide for 16 in FB MUX, and 384 in N divisor;

    125 in M divisor ;

    At this point I'm aspect that with my oscilloscope I can see output on Y0A ( 30,72Mhz ) syncronized with my 10Mhz That is a reference

    isn't right?

    In general I understund that I can use any frequenct for reference ; most important that value in PFD for primary and refernce freq are the same

    In this mode VCXO freq is syncronized with refernce freq

    My be I don't understund well and I thanke you very much for your kind and explain

    let me any and I try