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LMK04610EVM: not getting clock out

Adam Daluga
Expert 6385 points
Part Number: LMK04610EVM
Other Parts Discussed in Thread: LMK04610

Hello,

We are evaluating the LMK04610 but I am having issues with the evaluation module.  I’m using a 100 MHz source, and trying to get a 100 MHz output bypassing the VCXO.

 

I’m selecting either of these 2 modes:

 

When I look at the PLL2 Reference clock using the mux on the status pin, I see it.  But, I am not getting a clock out.

 

There is a bug when using the Frequency Planer where is doesn’t write the dividers to PLL1.  I got it to work by changing them using the PLL1 control screen.

 

What can I provide to help you help me?

Thanks,

Adam

  • 0
    TI__Genius 12560 points

    Hi Adam,

    Usually when there are no other outputs on LMK04610 it can be because the VCO-to-output buffers are disabled, the outputs are not enabled, the output formats are not specified, or the outputs are being held in a divider reset state due to a SYNC pulse.

    • Check PLL2_EN_BUF_CLK_BOTTOM and PLL2_EN_BUF_CLK_TOP (should be enabled)
    • Check OUTCHx_LDO_MASK settings (should be disabled for output enabled)
    • Check OUTCHx_DRIV_MODE is set to a value other than powerdown
    • Confirm SYNC state is not high based on SYNC pin settings and EN_SYNC_PIN_FUNC, INV_SYNC_INPUT_SYNC_CLK, SYNC_PIN_FUNC, and GLOBAL_SYNC settings
    • Confirm outputs are not set as SYSREF with some non-continuous pulse count

    If there still has a problem after making these adjustments, please provide the .tcs file (preferred) or the hex registers (if .tcs file is not available) with settings for review.

    Regards,

    Ajeet Pal