Other Parts Discussed in Thread: LMK61E2
I am using an LMK04828 to gernate clock and SYSREF for a 500 MSa/s ADC, with a 250 MHz clock to the ZYNQMP FPGA.
In the future I would like to be able to synchrnoise multyiple boards, but for now I am just trying to get one board working.
To allow for multiple boards I am using refclk frequency = SYSREF frequency with 0 delay mode.
For the single board use case I am using an LMK61E2 to generate a reference clock of 15.625 MHz to Clkin1, with CLKin2 connected to backplane connector for a multi board case.
My SYSREF frequency = 500MHz/32. = 15.625 = the reference frequency. I am using nested 0-delay mode.
I have 156.25 MHZ VCXO and and using the 2500 MHz internal VCO.
I have setup most of the register from the Export Hex of TICS Pro and then added some extra writes at the end for synchronisation, trying to follow the data sheet section 9.3.2.1.1
To check the phase I am using SYSREF in continuous mode, but plan change to pulser mode. For the single board tests I am triggering the pulse burst from SPI, but for a multiboard solution I will drive CLKIN0 to trigger SYSREF from the backplane connector.
I appear not to be accurately synchronising the clocks. Trying multiple attempts at running the same configuration, the phase relationship between SYSREF and the sampling clock varies.
I am trying to assert SYNC by toggling SYNC_POL, but after I negate SYNC_POL, the clock outputs appear to still be in reset until I set SYNC_DISx, which is not what I expect and earlier posts suggest that this does not gaurantee the timing of the reset across all channels. I don't understand why the outputs do not reset only while SYNC_POL=1, but actuall stay reset until SYNC_DISx=1
The full register write sequence is below:
Addr=0=0000, data=80 --- Reset stops clocks.
Addr=2=0002, data=00
Addr=256=0100, data=05
Addr=257=0101, data=55
Addr=258=0102, data=55
Addr=259=0103, data=01
Addr=260=0104, data=20
Addr=261=0105, data=00
Addr=262=0106, data=B0
Addr=263=0107, data=13
Addr=264=0108, data=05
Addr=265=0109, data=55
Addr=266=010A, data=55
Addr=267=010B, data=01
Addr=268=010C, data=20
Addr=269=010D, data=00
Addr=270=010E, data=F0
Addr=271=010F, data=13
Addr=272=0110, data=0A
Addr=273=0111, data=55
Addr=274=0112, data=55
Addr=275=0113, data=00
Addr=276=0114, data=20
Addr=277=0115, data=00
Addr=278=0116, data=F0
Addr=279=0117, data=11
Addr=280=0118, data=0A
Addr=281=0119, data=55
Addr=282=011A, data=55
Addr=283=011B, data=00
Addr=284=011C, data=20
Addr=285=011D, data=00
Addr=286=011E, data=F0
Addr=287=011F, data=11
Addr=288=0120, data=0A
Addr=289=0121, data=55
Addr=290=0122, data=55
Addr=291=0123, data=00
Addr=292=0124, data=20
Addr=293=0125, data=00
Addr=294=0126, data=F1
Addr=295=0127, data=05
Addr=296=0128, data=0A
Addr=297=0129, data=55
Addr=298=012A, data=55
Addr=299=012B, data=00
Addr=300=012C, data=20
Addr=301=012D, data=00
Addr=302=012E, data=F1
Addr=303=012F, data=05
Addr=304=0130, data=0A
Addr=305=0131, data=55
Addr=306=0132, data=55
Addr=307=0133, data=01
Addr=308=0134, data=20
Addr=309=0135, data=00
Addr=310=0136, data=B0
Addr=311=0137, data=45 CLKout12_FMT set . ClkOut12 restarts at this point, but not locked to input.
Addr=312=0138, data=00
Addr=313=0139, data=00 SYSREF_MUX=0 for basic sync functionality as manual 9.3.2.1.1 1(a)
Addr=314=013A, data=00
Addr=315=013B, data=A0
Addr=316=013C, data=00
Addr=317=013D, data=08
Addr=318=013E, data=03
Addr=319=013F, data=0D
Addr=320=0140, data=00
Addr=321=0141, data=00
Addr=322=0142, data=00
Addr=323=0143, data=91 SYNC_MODE=1, SYNC_EN=1, SYSREF_DDLY_CLR=1
Addr=324=0144, data=00 Clock Outputs stop. Removes Sync DISABLE.
Addr=325=0145, data=7F
Addr=326=0146, data=00
Addr=327=0147, data=18
Addr=328=0148, data=02
Addr=329=0149, data=02
Addr=330=014A, data=02
Addr=331=014B, data=16
Addr=332=014C, data=00
Addr=333=014D, data=00
Addr=334=014E, data=C0
Addr=335=014F, data=7F
Addr=336=0150, data=03
Addr=337=0151, data=02
Addr=338=0152, data=00
Addr=339=0153, data=00
Addr=340=0154, data=78
Addr=341=0155, data=00
Addr=342=0156, data=01
Addr=343=0157, data=00
Addr=344=0158, data=01
Addr=345=0159, data=00
Addr=346=015A, data=01
Addr=347=015B, data=D4
Addr=348=015C, data=20
Addr=349=015D, data=00
Addr=350=015E, data=00
Addr=351=015F, data=0B
Addr=352=0160, data=00
Addr=353=0161, data=02
Addr=354=0162, data=24
Addr=355=0163, data=00
Addr=356=0164, data=00
Addr=357=0165, data=10
Addr=369=0171, data=AA
Addr=370=0172, data=02
Addr=380=017C, data=15
Addr=381=017D, data=33
Addr=358=0166, data=00
Addr=359=0167, data=00
Addr=360=0168, data=10
Addr=361=0169, data=51
Addr=362=016A, data=20
Addr=363=016B, data=00
Addr=364=016C, data=00
Addr=365=016D, data=00
Addr=366=016E, data=13
Addr=371=0173, data=00
Addr=386=0182, data=00
Addr=387=0183, data=00
Addr=388=0184, data=00
Addr=389=0185, data=00
Addr=392=0188, data=00
Addr=393=0189, data=00
Addr=394=018A, data=00
Addr=395=018B, data=00
Addr=323=0143, data=B1 SYNC_MODE=1, SYNC_EN=1, SYSREF_DDLY_CLR=1, SYNC_POL=1..
Expect sync reset to start here.
Addr=323=0143, data=91 SYNC_MODE=1, SYNC_EN=1, SYSREF_DDLY_CLR=1, SYNC_POL=0
Sync removed but output does NOT start.
Addr=324=0144, data=FF SYNC_DISx set an all divider. Output restarts.
Addr=323=0143, data=10
Addr=313=0139, data=03 SYREF_MUX=3=Continuous, SYSREF output.
Looking at the signals as I write the SPI register
