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CDCM7005-SP: STATUS_VCXO and PLL_LOCK abnormal

Amy Luo
Expert 6890 points
Part Number: CDCM7005-SP

Hi team,

VCO indicators:

Output frequency: 384MHZ

Output power: 1.5 ~ 4.5dBm

Tuning voltage 0.5 ~ 2.5V

Voltage control sensitivity: 3-6MHZ / V

PLL settings:

Output clock: 384MHZ, 96MHZ, 24MHZ

Reference clock: 100MHz

Problem: the STATUS_VCXO pin of CDCM7005-SP of two of the six boards indicates abnormity at low temperature of - 10 ℃, and the locking indication is also abnormal. However, there is no problem with the output clocks of 384MHZ, 96MHZ and 24MHz of the test chip, which proves that the PLL locking is normal, and only the status indication is abnormal. No problem at room temperature.

The loop bandwidth is changed to 100k, and the problem still exists. 

What could be the problem？

Best Regards,

Amy Luo

  • 0
    TI__Genius 12550 points

    Hi Amy,

    Do you know, what is the phase detector frequency / feedback frequency used in their setup? Datasheet suggest feedback frequency should be greater than 2 MHz to get the correct STATUS_VCXO signal. otherwise frequency detection circuitry resets the STATUS_VCXO signal and PLL_LOCK signal to low.

    If they still see the issue,  suggest to share the used configuration files to look on it.

    Regards,
    Ajeet Pal