LMK05028: Configure LMK05028 so that it generates 644.53125MHz clock from IN3[10Mhz] input available from GPS

Hello Neeraj,

The reason OUT5's frequency goes to zero is because you are attempting to have a 390.625 MHz clock and 644.53125 MHz clock come from the same PLL. Since there is no common multiple of the two frequencies, the 390.625 MHz gets set to 0. Please change your clock outputs to look like below:

Please note I moved the 390.625 MHz clock to OUT0 because OUT[0:3] bank requires at least 1 clock from PLL2 for the DPLL calculations to occur.

The reason OUT7's frequency is not locking to 644.53125 MHz is most likely due to the DPLL1 not locking. I have preformed the run script calculations for the DPLLs, so now the frequencies should be locking to their target values.

Here is an updated tcs file with the changes I discussed above:

 6175.LMK_644_OUT7_390_OUT5_10Mhz_IN3.tcs

Please load this file into your TICS Pro and preform a soft-reset chip (as highlighted below).

Once you have completed this process, both frequencies should be locked to their target values.

Regards,

Kia Rahbar

Hello Neeraj,

First, check the status page and ensure the LOL_PLL1, LOPL_DPLL1, and LOFL_DPLL1 are not set. If they are cleared as shown below, then the issue is not due to the DPLL being unlocked.

If the above controls are cleared, then it appears that your frequency is 110545.45454 ppb off its target value. To remove this ppb error, you can enable the DCO mode shown in the image below and program the frequency step size to the target ppb shift required to shift the output frequency to its target value. Once you have written to the Freq. Step Size control, the FDEV will be automatically calculated. Then you can use the Incr/Decr buttons to shift the frequency.

Please note you also have the option to preform the Incr/Decr via registers or GPIO.

Regards,

Kia Rahbar

Hello Neeraj,

This means your DPLLs are not locking, thus leading to the inaccuracy in output frequency. Once you get the DPLL to lock then the outputs will be exactly 644.53125 MHz and 390.625 MHz.

The first step to ensure the DPLL is locking is to make sure a 10 MHz signal is actually being inputted into IN3. 

Then, make sure the correct clock input interface type is selected for the way you are providing the input to the device.

If that is not the issue then click update frequency plan and then click the run script button to calculate the appropriate DPLL settings. 

Once the calculations are complete press the soft-reset chip and then make sure the DPLL status bits are no longer high on the status page.

Regards,

Kia Rahbar