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CDCE925PERF-EVM: Questions about the output signals (and other related issues)

Garry Hanna
Prodigy 40 points

Part Number: CDCE925PERF-EVM

Our team has been evaluating the CDCE925PWR PLL-based clock generator chip for the last few weeks now, and we've been running into some issues we don't know how to resolve. 

First, when using an external power source, there is a persistent 1.2 kHz noise ripple at the input. Has anyone else encountered this? If so, is there a readily available solution? We were considering placing some additional caps on board to de-noise the input, but I wasn't sure where to put them if we did. 


Next, has anyone encountered difficulty with generating two signals with two separate PLL's from the same chip? The signals seem to "pulse" despite having similar output amplitude and frequency as the desired signal. We feel this is related to the phase noise we're experiencing when connecting the EVM board to our product board. 

Any and all help is appreciated! 

  • 0
    TI__Mastermind 18070 points

    Hello,

    If the noise ripple is on the input, then it's less likely from the clock chip itself. It's can be from the power source, external active components on test environment. 

    By "pulse" on the signal do you mean that the waveform is a series of pulses instead of a square wave? If that's the case, then something's wrong with resistor termination/impedance matching. If not, then what's the frequency of this pulse? Random phase noise shouldn't be deterministic.

    Regards,
    Hao

  • 0 in reply to Hao Z
    Prodigy 40 points

    Hi Hao, 

    Thank you for this reply. 

    Starting with the noise ripple, I can see multiple possible sources and I'll have to continue probing to isolate the issue. I will follow-up if I discover something. 

    I apologize for the confusion, I do not mean that the output is a square-wave/pulse. Instead, I am trying to say that the waveform doesn't settle to a clean, relatively stable Vp_pk (or frequency either). I can understand the frequency error, but I wouldn't expect that level of additional noise on the source since we added additional capacitance at the terminal pads. 

    Since you mention impedance matching, I want to clarify something from the scau022a manual. We did not install R2 and R4 because the description seems to only imply to do this if using a signal generator. Am I reading this incorrectly? We're using an external tcxo board. 

  • 0 in reply to Garry Hanna
    TI__Mastermind 18070 points

    Hi Garry,

    Sorry for the late response. I was out of office. You are right that R2 and R4 is not needed if the TCXO has an LVCMOS output. No termination is needed for LVCMOS input clock.

    Regards,

    Hao