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CDCUN1208LP: Clock & timing forum

Part Number: CDCUN1208LP

 Topic:  CDCUN1208LP 400-MHz  Buffer unused IN2 input
LVCMOS 3.3V Input in IN1 only.
8 differential 1.8 V outputs
3.3V LVCMOS clock input (16MHz) to IN1P (IN1N tied to GND).
We are not interested in using IN2 input (INSEL tied to GND).
What should we do with the unused input IN2?
IN2P, IN2N pins (floating/ tied to GND/ pull-down to GND/ pull-up to VDD/ other)?  
Current configuration
VDD 3.3V.
VDDO1-4 1.8V.
DIVIDE Floating
INSEL tied to GND
ITTP  floating
OTTP tied to GND
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