LMK04828: OSCout during powerdown

Hello Steve,

When the device is completely powered down there will be no OSCout. 

During the RESET condition, the OSCout will oscillate with 1.6 Vpp LVPECL output format as per default.

Regards,

Kia Rahbar

Hi Kia,

This should be made obvious in the datasheet, as I nearly created a problem in my design.

In the datasheet, it says that OSCout is available on supply powerup, so that an FPGA (say) has a clock to use before the device is configurured through the SPI interface. 

So, the implication would be that the FPGA would use the clock from OSCout for the SPI interface.

If the FPGA uses the SPI interface to access the powerdown register, then you say that the clock from OSCout will stop.

This will hang the FPGA because it has no clock. There is no way to access the SPI register to take the device of low power mode.

The only way to recover would be to physically power every down (switch off the power supply) and power it back up.

The datasheet should make the designer aware of the problem.

In my design I will  need an additional clock, which is not produced by the LMK04828

Hello Steve,

Thank you for pointing this out! We will make this update.

Regards,

Kia Rahbar