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LMK05318B: LMK05318B

Part Number: LMK05318B
Other Parts Discussed in Thread: , LMK05318

Hello Team,

Please can you help me to solve an issue with LMK05318B ?

We intend to use the circuit for cleaning noisy clock signal at 10MHz recovered at the end of a very long transmission. The circuit with it's analog PLL and the BAW VCO should be as a very good solution for that as described in the application report SNAA326.

For evaluation, I've got a LMK05318BEVM board with TICS pro firmware v1.7.2.0

 

Through the GUI:

DPLL is disabled in order to use AnalogPLL 1 only.

XO is set to 10MHz, single ended interface and I connect a 10MHz 0dBm signal to XO connector.

Outputs are set for 10MHz in setting output Frequency plan and  I can see the 10MHz signal on all activated output.

With the following configuration, Status0 LED are set on and off following the XO Input Loss of Signal, but I can’t find any solution to indicate PLL1 Lock Detected with status1 LED

I’ve tried to change the Raw registers but without any success.

 

In the 0xD register, the bits 2 (LOL_PLL1) et 4 (LOS_FDET_XO) are going to 1 when the I cut the 10MHz signal on XO, but without any change on status1 which stays at 1

 

When I change the frequency of the generator connected to XO, these bits remain high, this should indicate that PLL1 stays locked, whatever the frequency applied on XO connector ?

 

Notice that in all configurations and changes the signal remains present and stable at 10MHz on the activated output

 

Thanks a lot for your help

Christian

  • Hello Christian,

    Can you please save your configuration as a tcs file and provide it to me? Once I have received it, I will review it and provide you feedback on what could be the issue.

    To save your configuration as a tcs file, navigate to the tool bar at the top of TICS Pro and select file -> save (as shown below).

    Regards,

    Kia Rahbar

  • Dear Kia,

    Please find the tcs file of the project

    Essais LMK05318B.tcs

    Very Best Regards

    Christian

  • Hello Christian,

    In order to have the status1 LED reflect the PLL lock, you must use the setting called PLL1 Digital Lock Detect (DLD) (as shown in the image below). This is the correct setting for observing lock status.

    Regards,

    Kia Rahbar

  • Hello Kia,

    I thought DLD would correspond to digital PLL, whereas I only use APLL.

    I'm out of the office until next Monday, I'll test when I get back. I see will keep informed.

    Thanks a lot for your help

    Christian

  • Hello Kia,

    Thank you for your answer. When I set PLL1 Digital Lock Detect (DLD) on status 1, the pin goes high when the signal is applied on XO input.

    But  when I change the frequency of the signal applied on XO input,  this pin remains high while the PLL sould be unlocked ?

    Regards

    Christian

  • Hello Christian,

    After you change the frequency, can you please perform a soft-reset chip and then check status 1 again?

    If possible, can you also try turning off the XO input completely and seeing if that clears the status 1 state?

    Please let me know if either of these work.

    Regards,

    Kia Rahbar

  • Hello Kia,

    In all cases, Status1 remains high, this would indicate that PLL is locked while I can clearly see with oscilloscope and spectrum analyseur it is unlocked.

    When I turn off XO input, Status remains High.

    Best Regards,

    Christian

  • Hello Christian,

    Are you currently using the LMK05318 profile or the LMK05318B profile on TICS Pro?

    Could you also please try setting PLL1 Digital Lock Detect (DLD) on status 0 instead and see if that solves this issue? When I tested your configuration in our lab, I had PLL1 Digital Lock Detect (DLD) on status 0 and it was working properly for me.

    Regards,

    Kia Rahbar

  • Hello Kia,k

    I use LMK05318B profile, it is indicated so on the top line of the GUI.

    I ll try to move to status0, but I'm now out of the office. I think that I have already tried that, but I'll do it again and keep you informed of the result.

    I had a look at the Evalboard drawing and I can see the STATUS1 line is connected to the LED and to UA2GPIO11 also. Is it possible that U2 forces the line whatever the STATUS1 level ?

    Very best regards

    Christian

  • Hello Christian,

    Yes, please try status0 and let me know if that solves the issue.

    U2AGPIO11 is connected to the P5.0/A8/VREF+/VeREF+ pin of the MSP430. This pin is used as an output of reference voltage to the ADC, an input for an external reference voltage to the ADC, or an analog input A8 for the ADC. In the EVMs case, this pin is used as an input, so it should not be effecting the STATUS1 level.

    Also just to make sure, are you using the LMK05318BEVM or the LMK05318EVM? The pin/jumper/switch settings differ between the two devices.

    Regards,

    Kia Rahbar

  • Hello Christian,

    Yes, please try status0 and let me know if that solves the issue.

    U2AGPIO11 is connected to the P5.0/A8/VREF+/VeREF+ pin of the MSP430. This pin is used as an output of reference voltage to the ADC, an input for an external reference voltage to the ADC, or an analog input A8 for the ADC. In the EVMs case, this pin is used as an input, so it should not be effecting the STATUS1 level.

    Also just to make sure, are you using the LMK05318BEVM or the LMK05318EVM? The pin/jumper/switch settings differ between the two devices.

    Regards,

    Kia Rahbar

  • Hello Kia

     I confirm the board is LMK05318BEVM.

    When I use Status0 it seems working well. Slight smileI don't know why but the main is that I can use one of the Status output for checking in real time the locking state and the presence of signal on XO.

    Thanks a lot for your help.

    Best Regards

    Christian