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LMK04832: PLL1 NOT LOCKING

Manasa Jami
Prodigy 40 points
Part Number: LMK04832

Hi team

In our design we are using two LMK04832 Chips. One chip we are using as Master and another one as Slave. After loading registers in master chip both PLL's are locked .But for slave only PLL2 ls locking whereas PLL1 is not Locking.

But when tested on LMK04832 EVM both PLL1 and PLL2  locked with the same code as above.The loop filter design is different on board compared to EVM. Is this the reason why LMK04832 is not behaving as expected on our board.

I have attached the schematics and .tcs file used to program LMK04832. 

Slave_LMK.tcs

Slave_LMK.pdf

  • 0
    TI__Mastermind 33560 points

    Hello Manasa,

    The TCS file looks correct. If I can get the VCXO gain in kHz/V or in ppm/V, we can check the loop filter stability in PLLatinum Sim. Is it the same VCXO as the EVM?

    I do see that the SYNC_DISx bits are cleared - if you have a logic HIGH signal on the SYNC pin, this may be putting the outputs into a reset condition. You did not mention whether you have outputs on the slave device, so it could be possible that the SYNC pin state is causing a divider reset condition in the zero-delay feedback path and preventing PLL1 from locking in your system. You could try clicking the "All On" button for the SYNC disable bits on the SYNC/SYSREF page and see if this allows PLL1 to lock, but since you did not mention an absence of outputs I do not think this is the likely problem. Just something quick to check.

    Regards,

    Derek Payne

  • 0 in reply to Derek Payne
    Prodigy 40 points

    Hi DereK,

    Even though master LMK is not locking slave is locking. And in master we are getting CPout current of LMK IC is 3.2V but in evm we observed 1.5V with same code.We placed loop filter same as evm.

    We are unable to trace out problem in Master code .Even though we are giving reference clock externally using signal generator we observed same issue.

    I am sharing you master schematics and .tcs file.

    2350.Master_LMK.pdf6253.Master_LMK.tcs

  • 0 in reply to Manasa Jami
    TI__Mastermind 33560 points

    Manasa,

    The master file you provided is routing the feedback mux to PLL1, but the feedback mux is not enabled. You have a few options:

    1. Enable the feedback mux (FB_MUX_EN=1), set the FB_MUX source to CLKout6, and enable CLKout6 so that the FB_MUX has a source. Maybe you tried to do this but this is probably not what you actually want, unless you're trying to use the device in nested zero delay mode.
    2. Switch feedback sources to OSCin (PLL1_NCLK_MUX=0) and use the VCXO as feedback to PLL1. The PLL1 N divider would need to be changed to 120 instead of 240, since the VCXO is 122.88MHz. This puts the device in dual loop mode.
    3. Switch feedback sources to PLL2_P (PLL1_NCLK_MUX=2) and use the VCO prescaler output of PLL2 as the feedback source. While you could do this, I'm not sure it's what you want; it's a nested loop, but not a nested zero-delay mode.

    Regards,

    Derek Payne