SA555: Clock & timing forum

Nakai-san,

Our '555 expert is on holiday this week so I will try and assist you the best that I can. 

Q1. What is VCC range can Figure 11 Output Pulse Duration vs Capacitance graph on page 10 be applied for?

It isn't specified in Figure 11, but Figure 9 shows the circuit for Monostable Operation for which the graphs are applicable. Figure 9 shows VCC as 5 V to 15 V. 

Q2. I can see "Ra=10Mohm" in Figure 11 graph. Can 10Mohm be used for Ra when VCC is 5V in the worst case? I think RA should be less than 3.2Mohm when VCC is 5V because the capacitor placed between THRES pin and GND can not charged to the THRES voltage I think RA should be less than 3.2Mohm when VCC is 5V because the capacitor placed between THRES pin and GND can not charged to the THRES voltage through Ra in case of 4.2V THRES voltage level (Max value) and 250nA THRES current (Max value) through Ra in case of 4.2V THRES voltage level (Max value) and 250nA THRES current (Max value).

You are correct. If the threshold input current is at the maximum 250 nA limit the voltage drop across a 10 M RA there would be a 2.5 V drop across the resistor. The datasheet states in the notes under the 7.4 Electrical Characteristics table in note (1) "This parameter influences the maximum value of the timing resistors RA and RB in the circuit of Figure 12. For example, when VCC = 5 V, the maximum value is R = RA + RB ≉ 3.4 MΩ . ." Since there is only RA in the monostable circuit that would be about the limit. Less resistance would be better at this voltage level.

You might want to consider the TLC555 CMOS timer as its input current is in the tens of picoamps and the drop across RA will be much less. 

https://www.ti.com/lit/ds/symlink/tlc555.pdf

Q3. What is the maximum value of the capacitor placed between THRES pin and GND? Is there not limited? Or is it less than 100us which is the maximum value of Figure 11 graph to protect discharge transistor connected to DISCH(No.7)?

The timing capacitor is shown with a value up to 100 uF. That is certainly usable, but the issue becomes the quality of the capacitor. Many capacitor types that are available with a 100 uF capacitance have lossy dielectric types which looks like a high-value resistor across the capacitor. That loss resistance in conjunction with a high-value RA affects the timing of the circuit and introduces errors that make the timing less predictable. 

We have reviewed in the past the SA555 DISCH pin current when it discharges a 100 uF timing capacitor. The internal SA555 transistor that sinks the discharge current from a 100 uF timing capacitor is sufficiently sized to handle that current. 

Regards, Thomas

Precision Amplifiers Applications Engineering