Hi everyone,
I met a new problem when I config SYSREF signal with 'SYNC SPI (Pulser)' mode(Figure 1), but when I catch the signal the SYSREF changed like a spur with overshoot at the falling edge(Figure 2) although the device clocks are sync. When I disable the SYSREF, the siganl is normal(Figure 3). I don't understand why?
PS: I use 10MHz oscillator as PLL1 input.
Hi Nan Li,
Sorry there was an error in last comment, as SYSREF in pulser mode can be generated through SYNC_MODE set with SYNC SPI (pulser) setting and write the 0x13E register (click at send pulses) with the number of pulses.
When I disable the SYSREF, the siganl is normal(Figure 3). I don't understand why?
I am not clear on the SYSREF disable mode and get the SYSREF waveform. When SYSREF is configured in pulser mode, it should generate number of pulses mentioned in 0x13E register with send pulse command.
Would be great, if you can share the used configuration file for programming the device and will review the same.
Regards,
Ajeet Pal
Hi Nan,
Apologies for the delay, Ajeet is out so I'll take over for now.
The SYNC/SYSREF path is shared, so SYSREF signals can reset the divider and SYNC signals can buffer through to the SYSREF outputs. If you have SYNC_DISx bit cleared when you generate a pulse on the SYSREF pulser, it resets the other clocks. If you have SYNC_DISSYSREF bit cleared when you generate a pulse on the SYSREF pulser, it resets the SYSREF divider, which can cause the pulse to be too short. You should only clear the SYNC_DISx and SYNC_DISSYSREF bits when you are prepared to interrupt and reset the channel/SYSREF dividers for phase synchronization. After the initial SYNC event that establishes a specific phase relationship between device clocks and SYSREF, you should set the SYNC_DISx bits and SYNC_DISSYSREF to prevent the dividers from being reset on the SYSREF pulser event.
This might not be an issue, but for completeness: You can also use the SYSREF_GBL_PD bit to hold a SYSREF output low or at common mode voltage while a SYNC event is happening, to prevent the SYNC pulse from buffering out through the SYSREF outputs. This is effectively a "mute" control, so SYNC events at the LMK04828 do not accidentally get interpreted as SYSREF events at the devices to be clocked.
The divider reset procedure, which comes before using SYSREF and establishes phase relationships between device clocks and SYSREF, can be simplified to:
Once the dividers have been reset, the SYSREF triggering should be straightforward:
Regards,
Derek Payne
