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Original question:

LMK04806: LMK04806 phase noise degradation

LMK04806: Problems encountered in LMK04806 debugging

Gabriel Wang1
Genius 4715 points
Part Number: LMK04806

Dear Expert

1. The reads and writes of register R0 are inconsistent (write 0x00145000, read back 0x80000320), and the reads and writes of other registers are consistent.The order of writing to register is from top to bottom according to the following table.CLKoutX_Y_DIV and CLKoutX_Y_DDLY can't write to the R0 register.

2. PLL often loses lock in 0-delay mode.However, in normal mode, PLL has not yet experienced a loss of lock.There is no difference between the two except register configuration.What is the cause of this?And can the manufacturer give a set of recommended values for C1, C2, R1 (PDF=80MHz)?

  • +1
    TI__Mastermind 28550 points

    Hello Gabriel,

    Gabriel Wang1 said:
    1. The reads and writes of register R0 are inconsistent (write 0x00145000, read back 0x80000320), and the reads and writes of other registers are consistent.The order of writing to register is from top to bottom according to the following table.CLKoutX_Y_DIV and CLKoutX_Y_DDLY can't write to the R0 register.

    Please note, in TICS Pro, the purpose of the R0 (INIT) register is so that when you program all registers, it will also cause a device RESET by setting bit 17 of R0.  Then R0 register gets written with intended values on the next line.  So when changing CLKout_0_1_DIV and CLKout0_1_DDLY, you should see the changes on R0 register.  Do I understand changing these fields on the outputs page, does not update R0?  Note that other CLKout_X_Y DIV and DDLY will impact other Rx registers.  When mousing over a control, in the lower left you will see a context help that displays the register and location which will be updated.

    Can you tell me more about how you are doing the readback?  I notice the in the picture, the settings for R11/R12/R13 don't include any output pins as uWire readback.  Do you have any scope screen shots showing the timing of the readback?  Of course, that all other registers can readback is suspicious.  If you repeatedly read R0, do you still get the incorrect value?

    Can you elaborate more about what happens when you lose lock?  Do you see the PLL2_LD signal go low?  Do you measure an error in clock frequency?  Does the CPout pin voltage change significantly (rail high or low?).

    Gabriel Wang1 said:
    2. PLL often loses lock in 0-delay mode.However, in normal mode, PLL has not yet experienced a loss of lock.There is no difference between the two except register configuration.What is the cause of this?

    Is this intermittent for just a few seconds, the it locks again?

    Gabriel Wang1 said:
    And can the manufacturer give a set of recommended values for C1, C2, R1 (PDF=80MHz)?

    We could, however have you tried the PLLATINUMSIM-SW for loop filter design?

    73,
    Timothy

  • 0 in reply to Timothy T
    Genius 4715 points

    Dear Timothy

    Thanks for your reply!

    1.R0 write error has been solved, which was caused by incorrect write timing

    2. In 0-delay mode, PLL is often lost as follows

    (1) When the register configuration is complete, the indicator light of PLL2_DLD will flash

    (2) In the case of PLL lockout, the output frequency will be deviated.For example, if set to 1MHz, the output may be 1.03MHz

    (3) When PLL is out of lock, the output of loop filter usually contains AC component.As shown in the figure below

    (4) The values of R1, C1 and C2 of the external loop filter have little influence on PLL locking

  • 0 in reply to Gabriel Wang1
    TI__Mastermind 20900 points

    Hi Gabriel,

    could you please share a TICS pro file for your 0-delay register setting (File->Save).

    Do you use single loop or dual loop 0-delay?

    Regards,

    Julian

  • 0 in reply to Gabriel Wang1
    TI__Mastermind 20900 points

    Hi Gabriel,

    the settings looks correct.

    Here is a loop filter proposal.

    regards,

    Julian