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LMK05028: Read the phase difference between the inputs and output 1PPS

Phi Tu1
Prodigy 110 points
Part Number: LMK05028

Hello

We are currently using LMK05028 to generate 1PPS in 3 loop mode with 10MHz
OCXO and 48MHz XO from a 1PPS GPS and output 1PPS with ZDM.

Result: The DPLL is lock and ZDM started. I measured the output 1PPS and
input 1PPS. Its phase aligns.

We want to read the phase difference between the 1PPS input and 1PPS output
so I can know when output 1PPS and input 1PPS are aligned so we can start
our application correctly.

Could you help me out?

Thank you very much.

Tu

  • 0
    TI__Expert 8585 points

    Hello Tu,

    Once PLL is locked with ZDM enabled, the PLL will have minimal phase delay (phase offset) between its reference input and the output clocks. The input-to-output phase offset (tPHO) will be repeatable after exiting holdover, after a switchover event, and after device start-up. The typical tPHO is 2 ns as shown below.

    You can also readback the phase offset from the following registers.

    For DPLL1:

    DPLL1_REF_SYNC_PH_OFFSET can be used to readback the DPLL1 REF zero delay mode phase offset. DPLL1_REF_SYNC_PH_OFFSET is made up of the following registers: 0x18E[4:0], 0x18F, 0x190, 0x191, 0x192, 0x193. Below is an image of the LSBs. 

    For DPLL2:

    DPLL2_REF_SYNC_PH_OFFSET can be used to readback the DPLL2 REF zero delay mode phase offset. DPLL2_REF_SYNC_PH_OFFSET is made up of the following registers: 0x219[4:0], 0x21A, 0x21B, 0x21C, 0x21D, 0x21E. Below is an image of the LSBs. 

    These register can be found in the LMK05028 register map: https://www.ti.com/lit/ug/snau233/snau233.pdf?ts=1636125887948&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FLMK05028

    Regards,

    Kia Rahbar

  • 0 in reply to Kia Rahbar
    Prodigy 110 points

    Hello Kia

    I think the DPLL2_REF_SYNC_PH_OFFSET and DPLL1_REF_SYNC_PH_OFFSET are use to set an phase-offset between input and output if we want to control or calib phase. 

    I want is read the current phase between output 1PPS and input 1PPS from ZDM TDC. Can LMK05028 support it,

    Thanks

    Phi Tu

  • 0 in reply to Phi Tu1
    TI__Expert 8585 points

    Hello Phi Tu,

    Unfortunately, there is not a register to readback the current phase offset. With that being said, the input-to-output phase offset (tPHO) will be repeatable after exiting holdover, after a switchover event, and after device start-up. The typical tPHO is 2 ns.

    If you would like to know the exact phase offset, a manual measurement must be performed.

    Regards,

    Kia Rahbar