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LMK04832-SP: SPI 3-wire-timing - SDIO tristated in read-mode before/after CS' goes high

Bodo Rauhut
Prodigy 120 points
Part Number: LMK04832-SP

Hi all,

I have 3 questions regarding the SPI-IF of the LMK04832-SP:

1) The datasheet "SNAS698B – MAY 2020 – REVISED DECEMBER 2020" does not mention any timing-parameter in read-mode for SDIO before/after CS' goes high.
Or in other words: when will SDIO be tristated in read-mode (switched from OUT to IN) related to the rising edge of CS* (before or after CS* goes high)? 
Is there a dedicated timing-parameter for "SDIO-tristate when CS* goes high"?

2) May be this was already asked in this forum: what is the minimum time for "tdv" (max. 120 ns). I assume min-time for "tdv" would be 0ns?

3) In read-mode: when exactly does the LMK04832-SP switch the SDIO-line from IN to OUT?
I assume, it will be right after the falling edge when "D7" is placed on SDIO (assuming tdv_min = 0ns)?

Thanks a lot in advance!
Best Regards
Bodo Rauhut

  • 0
    TI__Mastermind 33690 points

    Bodo,

    1. We didn't specify the SDIO->tristate timing in the datasheet, but treat it as equal to tDV: 120ns maximum from CS* going high to SDIO tri-state. There's actually an undisclosed SPI streaming function which allows us to keep sending clocks after the initial 24-bit transaction, and the LMK04832-SP will start outputting the next register data (i.e. go from R0[0] to R1[7] on clock rising edge 25). Since we can keep streaming registers, it doesn't make sense to tri-state the output on a clock cycle trigger; it's purely based on CS* going high.
    2. In theory, minimum tDV is 0ns... in practice there's some minimum latency through the flip-flops and logic, which is normally around 10-20ns.
      1. "That's a long time to go through some logic gates" you may be thinking, and you're correct... but this is the LMK04832-SP, which uses latchup-resistant digital circuitry, so the underlying circuits are much bigger and slower as a result. By comparison, the commercial device is usually much less than 10ns.
    3. SDIO is switched from input to output on the falling clock edge between address[0] and data[7], which is the same moment you described. Again, assume minimum tDV is practically 10-20ns.

    In case it wasn't clear, you can actually disable 3-wire SPI mode and use 4-wire communication instead if it's easier for your system. The SPI_3WIRE_DIS bit in R0 controls whether SDIO will switch to an output during read transactions; meanwhile, the GPIOs such as STATUS_LDx, RESET, or CLKin_SELx can be switched to 4-wire mode with a single register write to toggle CLKin_SELx_TYPE to an output and CLKin_SELx_MUX to SPI readback.

    Regards,

    Derek Payne

  • 0
    Prodigy 120 points

    Dear Derek,

    thanks a lot for your answer!
    I have two replies to your answer:

    1) How will this "undisclosed SPI streaming function" be activated?
    Is there a "risk" of activating this SPI streaming function under normal functional operation conditions?

    2) "tDV = 120ns maximum from CS* going high to SDIO tri-state"
    --> in other words, I have to wait at least for tDV = 120ns before I again activate the OUT-function of SDIO (starting with the next SPI-cycle)
    --> this will also influence the min-time for CS* = high 
    --> in this case, the min-time for CS* = high would also be tDV = 120ns
    --> is this correct or is there another (timing)requirement which requires to CS* = high for a longer time than tDV = 120ns?

    Thanks in advance for your answer!
    Best Regards
    Bodo

  • 0 in reply to Bodo Rauhut
    TI__Mastermind 33690 points

    Bodo,

    1. SPI streaming function is technically always on. There are two bits in R0 register which impact SPI streaming: R0[2] which controls whether the address increments (1) or decrements (0); and R0[3] which prevents the address from automatically incrementing or decrementing when set, regardless of R0[2] state. If you use the SPI bus one 24-bit transaction at a time as suggested in the datasheet, then this SPI streaming function is fully transparent and you will never observe it in practice, since you will always manually configure the address of the register to be written and never move on to a subsequent register automatically. The only "risk" I could potentially foresee is if you somehow write/read an additional byte during a SPI transaction, in which case by default you will write/read the final byte to/from a register one address lower by default. I have had some customers in the past who were unable to configure SPI for 24-bit writes/reads due to peripheral limitations on their bus controller, but who could use 32-bit SPI; they needed to be aware of this behavior for avoiding errors on their 32-bit writes/reads to properly handle the final byte. If you can configure your controller's SPI peripheral for 24-bit transactions, this edge case can be ignored.
    2. Your inference is correct, minimum CS* high time is a result of the SDIO turnaround time and is 120ns.

    Regards,

    Derek Payne

  • 0 in reply to Derek Payne
    Prodigy 120 points

    Dear Derek,

    thanks a lot for your answer!
    I have two replies to your last answer:

    1) "SDIO is switched from input to output on the falling clock edge between address[0] and data[7],"
        --> question: in my application (FPGA) I want to switch the SDIO-pin from
             OUT to IN also right on the falling clock edge between address[0] and data[7],
             what is your opinion: is this sufficient to avoid any bus-conflict on SDIO,
             or should I switch earlier from OUT to IN?
    2) Is there any "device compatible" commercial part available which has the same 3-wire SPI-IF (probably also with an EVAL-Board)?
             (for this "device compatible" part, JESD-204B is not really required)

    Thanks in advance for your answer!
    Best Regards
    Bodo

  • 0 in reply to Bodo Rauhut
    TI__Mastermind 33690 points

    Bodo,

    1. Switching SDIO on the FPGA right on the falling edge between address[0] and data[7] should be fine, provided the FPGA can turn the bus around in significantly less than 120ns (I'd say an order of magnitude faster if possible). If the FPGA bus turnaround time is longer, you could also include a series resistor to limit current into or out of the I/Os. The maximum bus speed is only 2.5MHz, so even with a probably-larger-than-needed 1kΩ resistor and 100pF loading your signals would still be pretty square at 2.5MHz.
    2. I'm not sure I understand what you're getting at with this question. Are you asking about devices which can act as SPI controllers for this kind of 3-wire interface? I would expect this could be handled by tying SDI/SDO of the controller together and using open-drain interfacing (which is also supported by LMK04832-SP, including in 3-wire mode). And if the controller can tri-state its own output pin on a falling edge trigger, even a push-pull I/O stage could have the controller connect the SDI/SDO lines. I don't know of any controller that specifically supports 3-wire SPI; this feature was actually requested by a specific customer during development of the commercial device to reduce I/O routing in their own system, and they used an FPGA to manage the SPI interface as well. Since (as I mentioned earlier) classical 4-wire mode can be enabled with a single register write, keeping the 3-wire capability in the space-grade device was deemed the least effort from a design perspective.

    Regards,

    Derek Payne