LMX2594: Interpolation of CAPCTL and DACISET in full assist mode

Hi Josh,

Generally it should be possible to interpolate in full-assist mode the way you describe. As far as the mechanics of the VCO, the gain of the VCO does change a little with capcode (CAPCTL), so the slope of the interpolation may not necessarily be linear from VCOmin to VCOmax; but if you're storing calibration points every 5 MHz, every region between these two points will appear approximately linear. In practice, each capcode usually covers a range of at least ±40 MHz across the usable charge pump output tuning range. The tuning range per capcode extends beyond the limits set for Vtune-based lock detect though, so this doesn't necessarily mean you can correctly interpolate with 40 MHz steps. 5 MHz steps sounds very reasonable.

Expanding on the Vtune lock detect mechanism a little: LMX2594 monitors the Vtune voltage and has a high/low comparator threshold limit set about 200mV higher/lower than nominal ~1.25V. As the capcode center frequency gets farther away from the operating frequency, the Vtune voltage will shift more in one direction or the other. If you get too far away from the center of the capcode, you might fall outside of the Vtune comparator limits and lock detect won't assert (even though you are probably locked). The charge pump will also tend to get unbalanced toward the edges of the tuning range as the MOSFETs leave saturation (< 0.7 V, > 1.8 V), though this should always be at a point much farther than the lock detect threshold by design. So when I say "usable charge pump output tuning range", consider that between about 0.7 V and 1.8 V.

The DACISET values control the VCO amplitude, and also can be interpolated linearly. There's a lot more latitude on allowable VCO amplitude, since there's a lot of process margin built into the amplitude calibration for extreme corners. For a nominal device, having DACISET too high by ±10 codes isn't much of a problem. At some point, the amplitude will be too high and the oscillator transistor will stop behaving linearly, which can increase VCO phase noise. And if the amplitude is too small, the slew rate is lower and again the phase noise increases. Practically speaking, neither of these conditions (except possibly deep saturation of the oscillator transistor) is going to impact frequency lock. And with 5 MHz interpolation, you'll have more than enough resolution to accurately set DACISET value. You might even consider setting DACISET value over broader steps, such that you update capcode with interpolated 2.5 MHz steps but you only update DACISET with e.g. 20 MHz steps, to increase frequency hopping speed for short hops.

As stated in the datasheet, in the range of 11900 MHz to 12100 MHz (boundary from VCO4 to VCO5) there can be some issues using VCO assistance. It may not be possible to perform the interpolation as suggested in this range, since the exact boundary for the VCOs on either side of this range is process-dependent. Even full assist codes may not remain the same across PVT for this boundary. I recommend following the datasheet note for in 7.3.6.1 for this VCO boundary, or performing some kind of tri-temp calibration on this region specifically, if this frequency range is within your system needs.

Regards,

Derek Payne