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LMK04832: Synchronization LMK04832 with bench equipment using the 10MHz of the equipment

Christian borelli
Prodigy 20 points
Part Number: LMK04832
Other Parts Discussed in Thread: LMK05318

Hello

We would like to synchronize our bench equipment clock generator with your LMK04832. The equipment has a 10MHz clock (dirty) that is use to synchronize it with multiple other equipment. do the LMK04832 have any input for synchronization (phase) with external clock (not clean)?

thanks, christian

  • 0
    TI__Mastermind 28550 points

    Hello Christian,

    You can provide the 10 MHz input to the CLKin of the LMK04832.  Do be aware of slew rate input limitations.  Sine-waves at 10 MHz are typically too slow except for large amplitude which could be too high for the input buffer or could be clipped to meet the max input amplitude.

    The VCXO that you use with the LMK04832 will then dictate the type of output frequencies you will get with optimized performance.  For example, if you wanted to generate another 10 MHz output that's clean, you should use something like a 100 MHz VCXO.  This allows a good frequency relationship with the VCO so the PLL can operate in a low noise manner (high phase detector frequency).

    For example, the EVM has a 122.88 MHz VCXO.  So in your case, the 10 MHz is locked to the 122.88 MHz VCXO - APLL1 locking 122.88 MHz to 10 MHz with an integer PLL will have a low phase detector frequency - but that's ok, the loop bandwidth is narrow and this is where the jitter cleaning occurs.  Then APLL2 will operate with a high PDF. Possibly 122.88 MHz * 2 or 122.88 MHz depending on VCO frequency.  Then you can divide down to get your output frequencies.  Like 491.52 MHz for example.  But you won't get 10 MHz.

    With the 122.88 MHz  VCXO, you can still lock the VCO to a frequency like 3000 MHz, but you'll have a lower phase detector frequency and performance won't be as great.

    --

    You can also use a DPLL product such as LMK05318 for jitter cleaning too.  this has our BAW technology with a VCBO of 2.5 GHz.  This could be a great option for jitter cleaning too.  And since VCO frequency is 2500 MHz, dividing down to 10 MHz or other 2500 / n frequencies will have great performance.

    73,
    Timothy

  • 0 in reply to Timothy T
    Prodigy 20 points

    Hi Timothy,

       something is not clear to me, i need to use the LMK04832 to generate 983.04MHz and to make this clock coherent for the ADC we need to synchronize it with the signal generator use to test the ADC. To use this we need to use the 10MHz of the signal generator and make sure the LMK04832 will generate a clock in phase with the signal.

    With this scenario, do you think this will work?

    We have an evaluation board for the LMK04832  and we will try to to this if we understand the HW setup..

    thanks for you help.

    regards,

    Christian

  • 0 in reply to Christian borelli
    TI__Mastermind 28550 points

    So when you use the LMK04832 with a 10 MHz input and have a 983.04 MHz output and lock them together, then the frequencies will be locked so the "phase" will not move between the 10 MHz and 983.04 MHz except in that 10 MHz and 983.04 MHz are not well related.

    The GCD of 10 MHz and 983.04 MHz is 80 kHz.  So you could have a 10 MHz and 983.04 MHz edges aligning every 12.5 ms (80 kHz).  I can't imagine this is important to your system?

    Unless you have multiple LMK04832 and want the 983.04 MHz signals to be aligned?  Normally when aligning multiple LMK04832 devices you can use zero delay mode and feedback the output clock to the input.  However in this case the PLL1 R = 125 and PLL1 N = 12288 and this is the most reduced state.  This effectively means you have a /125 created 125 possible phase relationships between two different LMK04832 unless you SYNC in the R divider.  Fortunately you can SYNC the R divider with LMK04832.

    Hopefully this gives you some insight in what you need or do not need as the case may be.

    You may also find the app note on Multi-Clock synchronization to be use use.  Please note the two rules for ZDM Determinism in section 4.1.

    73,
    Timothy