I would like to ask a question how to use LMK5B12204.
Currently, we are using LMK5B12204 and are having an DPLL unlocked issue.
In our schematic, PRIREF is tied to FPGA to receive clock signal and to generate audio recovery clock.
However, FPGA clock signal is inaccurate so it may cause the unlocked issue.
Also, the accuracy of FPGA output is not able to improve due to FPGA IP specification.
Do you have any idea?
Can I solve by setting "DPLL Frequency lock detect/DPLL phase lock detect"?
Plan :
PRIREF input : 48 kHz SE / CMOS Slew Rate Detector Mode
SECREF input : Disable
output : 24.576 MHz
PLL1 : 2500 MHz
PLL2 : 6144 MHz
XO : 24 MHz SE(no term)
Enable DPLL/VCO1-Cascaded Mode
Status：
R13 Register=00h
R14 Register=C0h
R357 Register=28h
R367 Register=28h
R411 Register=04h
LOS_FDET_XO=0
LOL_PLL1=0
LOL_PLL2=0
LOS_XO=0
LOPL_DPLL=1
LOFL_DPLL=1
HIST=0
HLDOVR=0
REFSWITCH=0
LOR_MISSCLK=0
LOR_FREQ=0
LOR_AMP=0
PLL1_VM_INSIDE=1
PLL2_VM_INSIDE=1
PRIREF_VALSTAT=1
SECREF_VALSTAT=0
Best regards,
