We are using the LMK04828 to clock and synchronize multiple multi-gigabit ADCs and DACs.
Vendor-specified synchronization procedure involves several steps. The first one needs to be performed with continuous SYSREF, which is followed by a step requiring a pulsed SYSREF (pulsed via software) and then a step again requiring a continuous SYREF.
All references below are to the LMK0482x datasheet revised May 2020.
I plan to do the following:
a) Initialize the device to generate the required clocks (which includes setting the dividers and digital delays) and also set it up for generating a continuous SYSREF per datasheet sections 9.3.1, 9.3.2 (will also set up SYSREF divider and digital delays as necessary).
b) Generate a SYNC event (by toggling the SYNC_POL bit),
c) When need to switch from continuous SYSREF to pulsed SYSREF or vice versa - reprogram the following register fields:
SYNC_MODE, SYSREF_MUX, SYSREF_PLSR_PD
Note: the other fields in the associated registers (0x143, 0x139, 0x140) will be left as programmed initially in step a above.
I have the following questions:
a) Is the above mechanization correct? I obviously need correct clock to SYSREF phases in both the continuous SYSREF and pulsed SYSREF cases.
b) Am I correct to assume that, since changes to above register fields do not involve modification of dividers or digital delays, it is not necessary to generate a SYNC event after switching from continuous SYSREF to pulsed SYSREF or vice versa?
Thanks,
