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Original question:

LMK04806: LMK04806 phase noise degradation

LMK04806: TICS pro design review

Jerry Chen
Expert 5110 points
Part Number: LMK04806
Other Parts Discussed in Thread: CODELOADER

Hi team,

I‘m remote supporting a semiconductor tester project. Customer would like to input a 100MHz OSC to PLL2 through OSCin, powerdown PLL1, and set internal VCO to 2.4G, then divide to 12 channels of clean 100MHz CLKout. They have problem that the HEX configuration attached below doesn't achieve what they want. I can't take an onsite support, but just paper review. Could you pls take a look at the configuration? What I've seen is they should set the phase detector polarity for PLL2 positive.

Thanks.

Fullscreen LMK04806_TI FAE.txt Download 
R0 (INIT)	0x80160140
R0	0x00140300
R1	0x00140301
R2	0x00140302
R3	0x00140303
R4	0x00140304
R5	0x00140305
R6	0x11110006
R7	0x11110007
R8	0x11110008
R9	0x55555549
R10	0x9102410A
R11	0x3000100B
R12	0x0B0C00AC
R13	0x1302080D
R14	0x0200000E
R15	0x8000800F
R16	0xC1550410
R24	0x00000058
R25	0x02C9C419
R26	0xAFA8001A
R27	0x10001E1B
R28	0x00201E1C
R29	0x0180019D
R30	0x0200019E
R31	0x001F001F
 

  • 0
    TI__Mastermind 28550 points

    Hello Jerry,

    Actually the negative PLL2 phase detector polarity is correct.

    I looked over the config, it seems good.  Can you elaborate more on what is meant by "doesn't achieve what they want?"

    • Are there any clock outputs?
      • Could SYNC be asserted and preventing the output clock?  Try setting SYNC_POL_INV bit or changing pin state.
    • Are the outputs off frequency? By how much high or low?
    • Another debug point is checking the tuning voltage to the VCO by checking CPout2 voltage.  Sounds like you may not be able to do that, but...
      • Is it railed high or low?

    As a slide note, looks like CodeLoader is being used.  There is a more up to date software called TICS Pro.  However this is not the source of any issue.

    73,
    Timothy

  • 0 in reply to Timothy T
    TI__Mastermind 28550 points

    Jerry,

    I was just double checking the schematic again to look at the loop filter for PLL2.  It appears it is not connected.  It also seems to be labeled as if it was for PLL1 (CPOUT2_PLL1).  It is not.  Please refer to the datasheet figure 20 in section 9.1.1.2 for PLL2 loop filter information.

    73,
    Timothy

  • 0 in reply to Timothy T
    TI__Expert 5110 points

    Hi Timothy,

    Customer feedbacks that LMK04806 on their board can not output the 12 channels of 100MHz LVDS clockout. There is loop filter for PLL2. I attached the full schematics here.MAIN SCHEMATIC P04 Clock 100M.pdf

    They measured CPout2 voltage voltage, it was low, so we will focus on checking PLL2.

    I will apply an EVM to check the config, as EVM can report error through GUI. You could give comments if you see anything else that I can try.

    Thanks.

  • +1 in reply to Timothy T
    TI__Expert 5110 points

    Hi Timothy,

    We found there was error for the interface. We are working on that to make sure the config has been written into chips correctly.

  • 0 in reply to Jerry Chen
    TI__Mastermind 28550 points

    Ok, keep us posted.

    When they say their board can't output the 12 channels of 100 MHz.  Does that mean there is absolutely no clock output?  If no AC component, what is the DC component?

    Has this board ever worked?  If not check the supply voltage.  Also, if you can measure supply current, that can be a good indicator of what the part is doing (or not doing).

    73,
    Timothy