In my application,LMK00334 is used as clock buffer(one clock input and 2 clock outputs) for PCIE Gen5
The driver and receiver are all LP-HCSL but LMK00334 is HCSL
We are concerning for the communication of LP-HCSL to HCSL and HCSL to LP-HCSL
Could you provide your comments on this?
For example, could they communicate or not? Is there any risk or any concern technically?