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LMK05318B: Output divider sync from different PLL

Tim Hendrikx
Prodigy 25 points
Part Number: LMK05318B

We have the LMK05318B to produce several clock frequencies for our system, some frequencies for Ethernet devices, others for ADC sampling.

Not all frequencies can be derived from PLL1 (2500MHz), so we use PLL2 to generate another frequency (2751MHz).

We want to synchronize the output dividers of the output clocks even tough they have a different input clock from different PLL's (PLL1/PLL2)

In my view we can just Sync all output dividers and with this all output clocks will have their phase aligned to within one 2500MHz period (0.4ns + skew).

This will not be within the datasheet specification, but good enough for our purpose.

Is this possible in the way we assume this is possible?

  • +1
    TI__Expert 8585 points

    Hello Tim,

    You're reasoning is partially correct. To synchronize the outputs, the following controls need to be set as shown in the image below:

    1. Set all the CHx_SYNC_EN controls high to synchronize the output channel dividers.

    2. SYNC_MUTE should be disabled so that the output drivers are not muted during a SYNC event.

    3. SYNC_AUTO_APLL needs to be set high to enable automatic output SYNC after PLL lock.

    4. PLL1_P1_SYNC_EN needs to be set high to enable the PLL1 P1 divider channel synchronization (synchronization between all the outputs coming from APLL1).

    5. PLL2_Px_SYNC_EN needs to be set high to enable the PLL2 Px divider channel synchronization (synchronization between all the outputs coming from APLL2).

    6. Once the sync controls have been set, toggle the SYNC_SW control to assert the output synchronization.

    If you follow the procedure explained above, then all output clocks will have their phase aligned to within one 2500MHz period (0.4ns + skew).

    Regards,

    Kia Rahbar

  • +1 in reply to Kia Rahbar
    Prodigy 25 points

    Hi Kia,

    Thanks for your fast response, I do have some additional question:

    We need to keep some clocks on the PLL1 domain running undisturbed to the processor, there is also no need to sync those clocks.

    So I assume I can not Sync PLL1_P1 as this will disturb the output clock. PLL2_P2 is not used in our case, this only leaves PLL2_P1 that can be synced.

    As the outputs from PLLx_Px Dividers are >2500MHz in our case, I assume we can only SYNC the channel dividers and get the phase aligned to within one 2500MHz period (0.4ns + skew).

    Is this correct?

  • +1 in reply to Tim Hendrikx
    TI__Expert 8585 points

    Hello Tim,

    Understood. Yes, you can simply sync the channel dividers and get a phase alignment within one 2500 MHz period.

    Regards,

    Kia Rahbar