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LMK04832: request for design review

Kiran Kumar R
Intellectual 275 points
Part Number: LMK04832

Hi Team,

We are using LMK04832 in our design to generate reference clocks for high speed serial interfaces and for clocking FPGAs. we are using LMK04832 in single loop mode ( only PLL2). I request you to review the design and provide the feedback.

PFA the Zip file containing schematics in PDF, and also Ticspro and PLLatinum files for your reference.

We are using VCO0 of PLL2 at 2500MHz and input reference is 156.25MHz from a LVPECL Oscillator connected to OSCin of LMK. Since the PLL2 Pdf will be 156.25 providing better jitter performance at output. What are your recommendations on XO frequency?. Also please review the power section of LMK. 

LMK04832_ti_query.zip

--

Thanks in Advance,

Kiran

  • 0
    TI__Genius 12560 points

    Hi Kiran,

    Your design schematic look good and the configuration file also fine. 

    With the 2500MHz VCO frequency, all other required frequencies are possible except 41.66MHz. Ideally with 2500MHz VCO and channel divider value 60, you can get the frequency 41.666666...MHz, which is in some decimal. Can you ensure on the actual required frequency - 41.66MHz? 

    Below word file is updated with the feedback comments on the received schematic. You can follow the same.

    20211209 - TI HW_Review_Mistral-LMK04832-DesignRef.docx

    Regards,

    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Intellectual 275 points

    Hi Ajeet,

    Thanks for the update.

    Ajeet Pal said:
    With the 2500MHz VCO frequency, all other required frequencies are possible except 41.66MHz. Ideally with 2500MHz VCO and channel divider value 60, you can get the frequency 41.666666...MHz, which is in some decimal. Can you ensure on the actual required frequency - 41.66MHz? 

    Our maximum required frequency from those channels are 41.66MHz and actual required frequency can be anything between 40MHz and 41.666MHz.

    Regarding XO selection, is selected 156.25MHz is fine or do you recommend lower frequency?. Please confirm this. 

    As per Ti recommendation, 560ohm / 100ohm termination is added for all LVDS outputs based on receiver internal or external termination. Also loop filter values are updated as per the image in the attached document. 

    PFA the updated word file with customer feedback updated.

    20211209 - TI HW_Review_Mistral-LMK04832-DesignRef_customer_fb_updated.docx

    Our board is 3U VPX and we have tight space constraint to add ferrite beads for each power supply pins. Decaps are updated with same value as in EVM. Will there be a major performance degrade if we go with our design ( with few ferrite beads) ?

    Please let us know your thoughts on this.

    --

    Thanks in Advance

    Kiran

  • 0 in reply to Kiran Kumar R
    TI__Genius 12560 points

    Hi Kiran,

    Kiran Kumar R said:

    Our maximum required frequency from those channels are 41.66MHz and actual required frequency can be anything between 40MHz and 41.666MHz.

    Regarding XO selection, is selected 156.25MHz is fine or do you recommend lower frequency?. Please confirm this. 

    Based on your selected VCO0 frequency 2500MHz, it can generate the frequency between the 40MHz and 41.6666MHz.

    156.25MHz XO is good to generate the required frequencies, as it is integer division of selected VCO frequency.

    Kiran Kumar R said:
    Our board is 3U VPX and we have tight space constraint to add ferrite beads for each power supply pins. Decaps are updated with same value as in EVM. Will there be a major performance degrade if we go with our design ( with few ferrite beads) ?

    The LMK04832 contains internal voltage regulators for the VCO and other internal blocks. The clock outputs (Clock groups VCC pins) do not have an internal regulator, so a clean power supply with sufficient output current capability is required for optimal performance. Provided Decaps are good for noise filtering at each supply pin. But ferrite beads are needed to improve the crosstalk between the clock groups outputs. Ferrite bead can be eliminated or the clock group supply pins can be tying together for clocks out that share the same frequency or otherwise can tolerate potential crosstalk between outputs with different frequencies. 

    You can further optimize the clock out frequencies based on clock group and can remove (avoid) some of the ferrite bead, which shares the same frequency.

    Thanks!

    Regards,

    Ajeet Pal