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LMX2594: JESD204B Clock Solution for generating 122.88MHz using 10MHz Ref Clock

Gerald
Genius 9570 points
Part Number: LMX2594
Other Parts Discussed in Thread: LMK5C33216, LMK04832

Hi Experts,

May I ask for help? Our customer is looking for JESD204B Clock Synthesizer ICs which can generate Device Clock & Sysref Clocks at multiples & submultiples of 122.88MHz. They would be needing 14 to 16 LVDS Clock outputs. And want to generate 122.88MHz and 245.76MHz for their application using a 10MHz OCXO 10ppb stable clock. Please suggest TI ICs which they can use to generate 122.88MHz, 245.76MHz and its low frequency submultiples clock using just an 10MHz Reference Clock Input.

I tried to filter a selection of synthesizers from the link below but was not sure if LMX2594 or other devices from the list can fit his requirements.
RF PLLs and Synthesizers | Products | Clock ICs | TI.com

If none from the list fit, may I ask for your suggestion if do you know what can best fit for this? Thank you so much in advance.

Kind regards,
Gerald

  • 0
    TI__Mastermind 33720 points

    Hello Gerald,

    The high output count suggests you should be using something like LMK04832 or LMK5C33216.

    LMK04832 is a dual-loop PLL, with PLL1 acting as a jitter cleaner and frequency translation stage using a VCXO, and PLL2 acting as the frequency multiplier. The typical use case for LMK04832 involves configuring PLL1 with a 10MHz reference and 122.88MHz VCXO, then configuring PLL2 with the 122.88MHz VCXO as the reference and an integrated VCO at either 2457.6MHz or 2949.12MHz and dividing down to the required frequencies. LMK04832 has a single built-in, JESD204B-compliant SYSREF divider accessible from every clock output, which can be digitally delayed in half-step increments of the VCO frequency.

    LMK5C33216 uses a similar architecture, but can achieve better performance utilizing a high-Q BAW resonator at 2457.6MHz for PLL2. Instead of using some VCXO, the DPLL can use an XO at an unrelated frequency, even one with lower stability, to lock a fractional PLL loop onto the BAW resonator; and uses the DPLL to correct the error in the fractional PLL by shifting the N-divider fraction slightly to track out any PPM or PPB error, based on some highly precise reference source. So in this case, the 10MHz OCXO could be utilized as a DPLL reference, while another higher-frequency XO or TCXO with relaxed characteristics could be used as the XO reference to the APLL. While the BAW PLL can be utilized at all 16 of the device's clock outputs, the SYSREF can only be utilized from some of them, and the synchronization procedure is more complex. LMK5C33216 also has digital delay adjustment capabilities based on the VCO frequency.

    Direct synthesis of 122.88MHz/245.76MHz from 10MHz is not recommended, since the phase detector frequency would necessarily be very low (80kHz) for such a configuration. A possible exception is utilizing a PLL with an external VCXO and very low loop bandwidth. LMK04832 can be configured so that only PLL1 loop is running, and a 245.76MHz VCXO could instead be used with 245.76MHz distributed to the SYSREF divider and the clock output dividers. This reduces the power consumption and the added noise from the second PLL, at the cost of lower clock distribution frequency and less flexible digital delay. In any case, most of the purpose-built solutions to this exact problem involve using an additional oscillator somewhere in the PLL loops to manage frequency translation.

    Regards,

    Derek Payne