LMK04826: CLKoutX+/- (X=8, 9, 10 and 11) polarity issue

Hirano-san,

Apologies for the lengthy delay, the thread wasn't properly assigned to me and I didn't realize.

I tested the customer configuration on our EVM but I was unable to reproduce the results they observed with the output seeming to operate at reduced amplitude until a format register was rewritten. Combined with your initial remark that customer is using their own PCB, I wonder if there is a hardware issue. I see the affected outputs are all using LVDS format. There is a known issue with LVDS/HSDS output format on LMK04826 where the output does not start properly without a DC path for current between output P/N pins. See datasheet section 10.4.2 for additional description and diagrams.

If SYSREF_DDLY is set to a reserved value, the SYNC event may not propagate fully through the SYSREF divider before the reset is complete and the divider phase may be effectively random when the SYSREF_DDLY programmed delay expires. The phase of the SYSREF divider would essentially be randomized. I thought there could be other effects, but it seems unlikely that this would be related to the customer's observation about the clock outputs; reserved value of SYSREF_DDLY should just cause unpredictable SYSREF phase offset, not issues with output format amplitude.

Regards,

Derek Payne

Hirano-san,

Reprogramming the output format register should reload the output driver, which is independent of the digital divide or other circuitry that controls phase alignment. Even if they want to do phase adjustment, it should be possible before activating the LVDS output drivers.

Toggling from powerdown to LVDS can help restart the output driver with different DC loading conditions, but I can't say with certainty it will work in all cases. The trigger for this failed-start condition is when the output pin voltages are close to each other during startup, and do not drift apart to begin output buffer oscillation. Applying 560Ω as a DC current path between the pins helps force the pin voltages to diverge on startup. Usually toggling from powerdown to LVDS will also apply different enough DC voltages to the pins to force a clean startup, but in very rare cases some devices will still be stuck. The sequence you suggested can be used for debugging or prototype testing, but I would not recommend putting it into production. Figure 31 is a much better long-term solution.

Do you know if their receiver can operate at LVDS common mode levels? As long as the receiver can accept 1.25V common mode, they could remove the AC-coupling capacitors and replace with 0Ω, and then DC-couple directly to the receiver. This creates a DC current path on startup which prevents the failed-start condition, does not add unnecessary load impedance and amplitude loss to the LVDS signal, and only requires a BOM change in most cases.

Regards,

Derek Payne