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LMK04208: Confirmation about holdover function

Ryotaro Fukui
Intellectual 2345 points

Part Number: LMK04208
Other Parts Discussed in Thread: LMK04828, LMK04832

Hello team,

I have some confirmation about the holdover function of LMK04208.

We are considering same 2 clock source inputs to CLKin0 (10MHz from OCXO) for redundancy and switch them while operation.

Question 1: During the switching period, can the holdover function produce the same output as before to CLKout without any instantaneous disconnection?
Question 2: If the above is possible, for how long can the holdover function retain the output of CLKout?

Please contact if there are any other information needed.

Best Regards,

Ryotaro Fukui

  • 0
    TI__Mastermind 34810 points

    Hello Fukui-san,

    Are you talking about using an external switch in front of CLKin0 input, and toggling the switch to change back and forth between two 10MHz OCXOs?

    I will assume this is the correct interpretation in my answers below.

    1. The automatic holdover feature requires a trigger to activate, which is usually PLL1 loss of lock. If PLL1 loses lock, there will be a temporary phase hit, which will show up on the output as phase error. You could use pin mode or register settings to trigger holdover manually before a clock switching event, which will greatly reduce any phase error during the switching event. Then you could release holdover and select CLKin0 again to lock to the redundant source after the switch event is complete.
    2. The LMK04208 includes a 10-bit DAC with a tracking feature and history collection that can sample the voltage at the charge pump output and output the same value during holdover. The DAC range is nominally 0V to 3.3V, so each code has about 3.2mV of resolution. The gain curve of the VCXO (in ppm/V) multiplied by the worst-case error of one code, should give you the worst-case error for the VCXO and for the frequency accuracy of CLKout. For instance, if your VCXO has 20ppm/V adjustment range, this implies 3.2mV * 20ppm/V = about 65ppb error worst case for an accurate history sampling of the DAC.

      In theory this holdover state could be maintained indefinitely. In practice, the ambient temperature and the VCXO temperature will change, which will change the output frequency non-linearly by some small amount. If system temperature can be kept very consistent during the holdover state, error can be very small; but if temperature changes, error will increase as well.

    Why does the customer want to use two redundant inputs with a switch on CLKin0, instead of using both CLKin0 and CLKin1? LMK04208 supports automatic clock switching between CLKin0 and CLKin1, but it would not be a "hitless" switch - there would be phase error during the switching period. Are they trying to avoid a phase hit when switching to a redundant clock? We have other jitter cleaner devices such as LMK04828 or LMK04832 which can support "hitless" switching between clock inputs as well.

    Regards,

    Derek Payne