• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 21 subscribers
  • Views 363 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMX2592: LMX2592

Dror Ben Yehuda
Prodigy 30 points
Part Number: LMX2592
Other Parts Discussed in Thread: LMX2594

We have a multiple boards structure where each board has its own PLL (LMX2592). the RefClk is common to all boards but the number of clock buffers for each board is different.

in the example below, you can see that PLL #2 get RefCLK after passing 2 CLK Buffers while for PLL #1, it passes only 1 CLK Buffer.

we are using the PLL in Integer Mode only!

Questions:

1. Given the input phase to the 2 PLLs varies over temperature due to the clock buffer (phase variance changes between the 2 PLL inputs) what will be the phase variation at the output of the 2 PLLs

    example: if the PLL RefCLK phase changes (over temperature) by 1Deg (due to changes in the clock buffer), what should be the expected phase changes in the PLL output? is it 1Deg as well or 1Deg times Fout/Fin

2. Given we will swap to the LMX2594 (with the SYNC input), can we overcome this none controled phase difference?

  • 0
    TI__Guru** 111720 points

    Hi Dror,

    I think it is more convenient to use time instead of phase to estimate clock alignment.

    Assuming the time delay between A&B is tAB, then the delay time between A&C is equal to tAB+tBC.

    Similarly, the delay time between A&F will be tAD+tDE+tEF.

    When the PLL is locked, there is a time delay between its input and output. In integer mode, this delay time is basically fixed. So tBC = tEF.

    The input/output of the buffer also has some time delay. If we ignore the skew between B&D, then tAB = tAD. The time difference between C&F is therefore equal to tDE.

    We can continue in this way to estimate the time variation due to temperature.

    The phase SYNC feature of the LMX2594 works only when all the LMX2594 devices are sharing the same reference clock. In the above system diagram, the reference clock of the second PLL is not taken from D, so the SYNC feature will not be able to eliminate the delay due to the buffer.