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LMK03318: Interfacing w/ a DSP: Transition questions

Part Number: LMK03318
Other Parts Discussed in Thread: TMS320C6657

Hey team,

Couple questions:

If I initialize the LMK03318 clock generator in LVCMOS mode with the outputs on channel 0 disabled (I believe the outputs will tristate in LVCMOS mode), can I then transition them to LDVS mode, and if so what are the consequences of that operation?


The second thought I had regarding the LMK03318 is not powering the VDDO_x pins of the output channels going to the DSP until I bring up the CVDD of the DSP, is that a possibility with the clock generator chip?

If it's helpful information, the DSP is the TMS320C6657



  • Hi Cameron,

    You can just power down channel 0.


  • Hey Hao,

    With channel 0 powered down, would there be any issue transitioning from LVCMOS mode to LVDS mode?

    With regards to the second question, I imagine that the VDDO_x pin output can be controlled by enabling and disabling register 30 ?

  • From my understanding of the LMK03318, it outputs primarily 1.8V LVCMOS w/ two pins that have the option of outputting 3.3V LVCMOS. I think this is specified in section 8.1.3 of that datasheet?

    That being said, for AC-LVDS communication it is between 0.15 and 0.35.

    Am I understanding this correctly? It seems like the answer is that it will damage it no matter which communication protocol is used. The Jacinto team said anything w/ an LVCMOS common mode voltage greater than 0.3V would damage the device.

  • Hi Cameron,

    When the channel is powered down, there is no output. So it doesn't matter which output format you select. This device can only output 1.8V LVCMOS and cannot output 3.3V CMOS, unless you use the status pins to generate clock signals. I'm not sure I understand the 0.3V portion of your description. Do you mean common mode or swing? 0.15-0.35V is the swing of AC-LVDS. If AC coupled, common mode is 0.