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Original question:

LMX2592: Reference Input Power Recommendations

LMX2592: Ideal Vppd and ideal reference power to optimize phase noise

Cameron Wutzke
Expert 3937 points
Part Number: LMX2592


Hi all!

I see from the datasheet, As long as the Vppd falls between 0.1 to 1 for a differential signal, or 0.2 to 2 for a single-ended signal, the device will operate as defined on the datasheet. 

From customer's experience with other PLL designs, there can be a sweet spot in the input power range that has a small effect on the performance of the device. Right now they use a 100MHz crystal but there is an opportunity to change it to a 150MHz version. In either case, there's option to adjust the reference power into the LMX2592 if it was determined that there was an optimal range of input powers.

  • +1
    TI__Guru** 111720 points

    Hi Cameron,

    We did not do a full analysis on input level vs performance, we do not know if such a sweet spot exist. However, the input level actually affect the signal's slew rate, which is important to the PLL. For example, with a 10MHz clock, there is a huge difference in PLL performance between a sine wave and square wave clock. A LVDS (square wave clock, 400mV) will return good PLL performance but the sine wave clock, with the same amplitude, will return bad PLL performance. It is because the slew rate is very bad. We can increase the amplitude of the sine wave signal to increase its slew rate, this will improve PLL performance. 

    Slew rate improvement with higher signal swing is significant at low frequency, at higher frequency like 100MHz or 150MHz, the improvement is very limited as the slew rate is already good. The benefit of moving the input from 100MHz to 150MHz is we could have a higher fpd. At higher fpd, N divider value is smaller. As a result, PLL noise is smaller.