Hi,
I would like to ask if it is possible to sync two PLL which has two different frequency?
In our case it is 5.2 GHz and 7.6 GHz.
Best regards,
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi,
I would like to ask if it is possible to sync two PLL which has two different frequency?
In our case it is 5.2 GHz and 7.6 GHz.
Best regards,
Andri,
It is possible to configure these devices such that each one is frequency-locked and phase-locked to the same reference source, so in the most straightforward sense it should be possible to establish some repeatable phase relationship between the two outputs. But it is likely not possible to predict a priori what the phase error will be between the 5.2GHz clock and the 7.6GHz clock, when sampled at some integer divisor rate of both clocks (e.g. 400MHz).
You could take a measurement to determine the phase error between the 5.2GHz and 7.6GHz clocks when sampled at some common rate (e.g. 400MHz), and then remove this error using the MASH_SEED. This would place your synthesizers in fractional mode, so there will probably be some small performance penalty - but for smaller adjustments (step size ~1ps) the size of the denominator will be small, and the impact from the fractional divider will be minimal. Additionally, this adjustment strategy may introduce fractional spurs (which can be simulated using PLLatinum Sim).
Although you could trim the error between two measured devices, the part-to-part differences in input-to-output skew will vary considerably (on the order of 20ps) at similar voltage and temperature, and could vary even more across temperature (around 65ps). If your devices are at similar temperatures, they will skew together and share similar temperature coefficients. Voltage coefficient tends to have minimal impact since there are many internal LDOs setting lower internal voltages for critical path circuits. So the big source of error is some unknown input-to-output skew that will vary device-to-device based on uncontrollable process difference, and variation in configuration settings between devices (e.g. 5.2GHz uses the divide-by-2 path, whereas 7.6GHz is direct from VCO). It is nice to have a knob to turn such as the MASH_SEED adjust, but you will need a procedure to measure the error in the first place. We (TI) generally don't make a recommendation for how to do this, because it varies greatly from system to system. Common strategies include combining the outputs and tuning to the highest power, or performing some kind of ADC/DAC-based calibration farther downstream.
Regards,
Derek Payne