Start up time CDCE949

Rejeesh Raj

Other Parts Discussed in Thread: CDCE949

I wish to know the Propagation Delay of the chip "CDCE949" for PLL enable mode that is the time for outputting the programmed clock.

In details the delay is, in giving a programmed output clock after the power rails are settled and the input reference clock is stable.

over 14 years ago

0 Georg over 14 years ago

TI__Intellectual 950 points

Raj,

the propagation delay time at PLL bypass (disabled) is typically 3.5ns. In case of PLL enabled, you need to add the lock time of the PLL. The PLL lock time varies over the PLL setting and can add to several 10 us.

Regards,

Georb Becke.

Clock & timing

Clock & timing forum

Start up time CDCE949