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LMX2820: Input OSCIN mode for best Phase Noise performance

Matteo Ricci
Prodigy 240 points
Part Number: LMX2820


Hi,

I am using the LMX2820 in a new project. The input reference clock is 100 MHz with input power > 10 dBm. This reference clock is sent to power divider with insertion loss about 8 dB.
So the reference clock input power to the LMX2820 is about 5 dBm.

What is the best configuration for the input reference clock  to get good Phase Noise performance?

1. Single ended or differential mode? 
2. Sine wave or pulse wave?
3. The slew rate for a differential input is bigger than single-ended input. It's correct?
4. How much does the slew rate impact on phase noise performance?

Thank you in advance.
Best regards.

Matteo Ricci


 
  • 0
    TI__Mastermind 33800 points

    Hi Matteo,

    The strategy for improving phase noise of the reference is almost always the one that maximizes slew rate, up to the point where the reference noise cannot be improved or the PLL noise is dominant.

    1. Generally differential signals will always be better than single-ended signals where possible. Single-ended signals converted to differential near the device through a typical balun will have a net benefit from the increased OSCin slew rate relative to any per-pin amplitude reduction (unless the balun insertion loss exceeds 3dB). Fully differential signals will have the advantage of better common mode noise rejection as well; this may not be an issue in many designs if the reference trace is short or properly shielded.
    2. Pulse wave such as LVDS or LVPECL tends to have better slew rate than a comparable sine wave. Sine wave slew rate maximum is given by SR = 2π*f*Vpk, while pulse wave slew rate can be mostly decoupled from signal frequency and amplitude. Note that OSCin duty cycle should be 50% if using the doubler.
    3. Correct, differential slew rate is usually higher than comparable single-ended slew rate. If you have a 100MHz sine wave at 5dBm, this is about 0.562Vpk into 50Ω and translates to a single-ended slew rate of 0.35V/ns. Assume a close to ideal balun, each output will have a 3dB amplitude reduction and see about 0.4Vpk into 50Ω. This translates to a slew rate of 0.25V/ns, but on both OSCin pins for a combined slew rate of 0.5V/ns. So for a lossless balun, per-pin amplitude is reduced by a factor of sqrt(2), but overall slew rate is improved by a factor of sqrt(2). 

      There are exceptions. A square-ish wave decomposes into a fundamental and several odd higher-order harmonics; if the balun bandwidth does not include several of the harmonics required for high slew rate on a pulsed waveform like LVDS or LVPECL, this can actually degrade the overall slew rate. But most of the time, these pulsed wave formats will be fully differential to begin with. This does occasionally comes up with single-ended LVCMOS though.
    4. I don't have exact numbers for you. Anecdotally, it helps to have at least 0.5V/ns slew rate. 8dBm single-ended or 5dBm into a balun at 100MHz is a good baseline for an acceptable slew rate. For a really fantastic reference there are great diminishing returns to increased slew rate, since the close-in noise becomes limited by the PLL 1/f and the far-out noise is rolled off by the loop filter. For a lower quality reference, the reference close-in noise itself may become the limiting factor, and slew rate improvements will not change the fundamental close-in characteristics of the reference. My point is, optimize as much as possible for slew rate, but don't optimize for slew rate at all costs as the benefits above maybe LVDS or LVPECL slew rates tend to be marginal.

    Regards,

    Derek Payne