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LMK5C33216: PLL programming

Jonathan Kolbrak
Intellectual 500 points
Part Number: LMK5C33216

Hello,

I'm using APLL1 and APLL2 of the LMK5C33216 for different clocks to FPGA's and data converters.  If PLL2 is reprogrammed to change the output configuration/dividers, etc, will this cause any interruption in the PLL1 and it's outputs.  I'm assuming that the SYNC for this PLL1 related outputs will not be enabled and no registers related to PLL1 will be written to during a change to the PLL2 and it's outputs.

Thanks,

Jon

  • +1
    TI__Mastermind 28550 points

    Hello Jon,

    Correct.  When a SYNC operation is performed, only the dividers with SYNC enabled will be reset.  In this way you can re-configure one PLL without impacting the other two.

    The dividers with SYNC enable include the VCO post dividers on the APLL page, such as PLL2_VCO_DIV_SYNC_EN.  And then the divides on the output divides themselves such as OUT_x_y_DIV_SYNC_EN.

    So be sure to set all SYNC_EN you don't want touched to 0!

    You can then also cause individual resets vs. full chip 'soft-chip' reset by toggling the DPLLx_SWRST and APLLx_SWRST on the User Controls page under "Control".  Just to the right of the SYNC_SW bit.

    73,
    Timothy