Hello,
I have a clarification on the CLK2/3 and 14/15 of the LMK5C33216. I understand that there is no SYSREF generation on those clock groups. I do see there is “OUT3 ChanDiv Static Offset. Static offset code which delays the output of the channel divider.” I can’t find I the datasheet how much that digital delay can be and are they also measured in VCO half-cycles?
Thanks,
Jon
