Hi,
As per other posts - CDCE for the default and my programming is not providing clock signals despite the input clock whih is a CMOS being adequate.
Again as per other post the Pin 19 TESTSYNC is connected to 3.3volts via 47k resistor in error.
Pin 20 REG_CAP3 is at 2.9volts.
I have implemented 4 separate power supplies - each 500mA for each side of the CDCE62002 - i designed the PCB based on the datasheet current at the time which did not state the preferred groupings. In fact the preferred groupings require power connections to opposites of the chips in some instances.
If Pin 19 TESTSYNC is tied to logic 1 (3.3volts) cause the CDCE62002 not to function correctly, and as such is the reason for the 2.9volts at REG_CAP3 ??
Again, i was working to an earlier datasheet - there was no indication of what to do with this pin - hence tied high with 47k resistor.
Thanks and regards,
Richrd.
