• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 21 subscribers
  • Views 578 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04610: Reference input to output apparent phase wander

Paul Roberts1
Prodigy 40 points
Part Number: LMK04610
Other Parts Discussed in Thread: LMX2594, , LMK04616, LMK04832

Dear TI Clock and Timing Team,

In our application we are using the LMK04610 as a jitter cleaner to clean a 128 MHz reference frequency, in combination with an external 128 MHz VCXO. The LMK04610 is used in PLL1 only mode to clean the reference frequency using a BW of about 10 Hz. The 128MHz outputs of the LMK04610 then provide the clean reference to separate external synthesizers to produce 4.096 GHz (LMX2594) sampling clocks, and is also divided in the LMK04610 to give SYSREF signals, which feed high speed 4GS/s ADCs. We have multiple of these boards that need to be synchronized.

In our application of multi element phase array receiver it is critical that the phase of multiple boards and the 4 GHz sampling clocks are precisely stable. Given the sample period is about 250 ps we need stability of order 10s of ps at constant temperature, which we do achieve with other typical PLLs in previous designs.

We are seeing, though, that the phase delay between the ref input and the output of the PLL1 jitter cleaner appears to wander randomly on sub Hz time scales, in contrast to what you would expect of a phase locked loop? When multiplied up to 4 GHz this causes large changes in phase between input and output and between multiple boards. On investigating deeper we believe it is the LMK04610 PLL1 itself that appears to have the wander.

On searching the forum today for clues I came across this comment by a TI employee regarding the LMK04610 PLL1.

" in reply to HeHa
TI__Mastermind 22920 points

Hi HeHa,

We redesigned the LMK0461x phase detectors to use a lower power architecture, but we discovered in validation that PLL1 phase detector does not track out wander very well at low loop bandwidths. We find that the absolute input-to-output phase of PLL1 wanders by ±2ns at <1Hz offsets, even at constant temperature, due to some underlying architecture effects. We did not want to offer a nested zero-delay dual loop mode if the input-to-output propagation delay variation was going to change by ±2ns. "

Could you please verify and confirm if this is in fact the case that the current production LMK04610 devices do indeed have a 2 ns phase wander in the PLL1? As you can appreciate a potential 2ns wander of a 7.8ns period 128MHz reference clock is large and when multiplied up to 4GHz causes multiple periods of phase shift and so is unsuitable for our design and will require board redesign. So I'd like to know for certain, or if there is a fix, so we can proceed accordingly

Thanks and regards,

Paul

  • 0
    TI__Mastermind 33790 points

    Hi Paul,

    Indeed, LMK04610 and LMK04616 still exhibit this wander in current silicon PLL1, and there is no workaround as this is somewhat fundamental to the semi-digital PLL architecture. While the architecture did what we wanted it to do in most cases (reduce the external loop filter components to none in many cases, and support even lower loop bandwidths than traditional architectures), one of the side effects is degraded wander response when the loop bandwidth is very low. 

    I would not recommend attempting to use LMK0461x for this kind of tight phase alignment if PLL1 is going to be involved. PLL2 does not exhibit these issues, so if only PLL2 is used, or if an external jitter cleaning PLL is used for the 128MHz VCXO and the LMK0461x output is brought back to the feedback of this external PLL in a nested zero-delay configuration, you can still get very tight phase alignment between input-to-output phase of two copies of the circuit. If the jitter cleaning should be integrated in the same device, the LMK04832 is the device we usually recommend for very precise phase alignment in nested zero-delay mode.

    Regards,

    Derek Payne (the very same)

  • 0
    Prodigy 40 points

    Thanks Derek for the prompt reply. 

    I'll have to investigate the LMK04832 alternative it looks like. So it uses a more "normal" PFD and loop filter in the PLL1 with possibly some external filter components needed?

    You mentioned the 04610 suffers wander when the loop bandwidth is "very low" . Is there a BW above which is no longer occurs, or does it just reduce somewhat with BW but still going to be too much for my requirements?

    Paul

  • +1 in reply to Paul Roberts1
    TI__Mastermind 33790 points

    Correct about LMK04832 PLL1 - it's a traditional PFD and loop filter design.

    For LMK04610, "very low" loop bandwidth on PLL1 applies to the entire reasonably achievable loop bandwidth of PLL1.