Please can provide assistance in the configuration for the LMK04610.
The Input clock is (CLK0) 10MHz. The External VCXO is 122.88MHz. The output clock is 122.88MHz.
Currently, PLL1 didn't lock of 10MHz of the input clock. If the input clock changes to 122.88MHz that is PLL1 locked.
What are the correct settings for the input clock 10MHz in this case?
Thanks in advance!